Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23958308	5709	0	0
EscTimeoutStoppedByClReset_A	23957706	3417743	0	0
EscTimeoutTriggersReset_A	4913309	325	0	0
RomAllowActiveState_A	23957706	58520	0	0
RomAllowCheckGoodState_A	23957706	58570	0	0
RomBlockActiveState_A	23957706	28284	0	0
RomBlockCheckGoodState_A	23957706	412704	0	0
RomIntgChkDisFalse_A	23957706	23326741	0	0
RomIntgChkDisTrue_A	23957706	108140	0	0
RstreqChkEsctimeout_A	23957706	4555	0	0
RstreqChkFsmterm_A	23957706	160	0	0
RstreqChkGlbesc_A	23957706	4555	0	0
RstreqChkMainpd_A	23957706	991429	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23958308	5709	0	0
T13	825	6	0	0
T16	3463	0	0	0
T27	0	55	0	0
T80	94153	0	0	0
T81	3008	0	0	0
T82	1766	0	0	0
T90	2656	0	0	0
T97	0	11	0	0
T100	0	56	0	0
T102	0	55	0	0
T104	740	7	0	0
T105	18530	0	0	0
T106	5282	0	0	0
T155	0	121	0	0
T156	0	54	0	0
T157	0	144	0	0
T158	0	116	0	0
T159	4168	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	3417743	0	0
T1	763	11	0	0
T2	59018	12850	0	0
T3	1979	51	0	0
T4	148985	15895	0	0
T5	1365	23	0	0
T6	2087	271	0	0
T7	1717	36	0	0
T8	1809	36	0	0
T9	1850	122	0	0
T10	6404	1450	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4913309	325	0	0
T11	224	2	0	0
T12	0	4	0	0
T13	0	4	0	0
T15	516	0	0	0
T20	85141	0	0	0
T34	698	0	0	0
T35	561	0	0	0
T36	1093	0	0	0
T39	1212	0	0	0
T40	708	0	0	0
T78	214	0	0	0
T79	1891	0	0	0
T97	0	3	0	0
T99	0	4	0	0
T100	0	3	0	0
T102	0	3	0	0
T104	0	5	0	0
T155	0	3	0	0
T156	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	58520	0	0
T1	763	3	0	0
T2	59018	91	0	0
T3	1979	6	0	0
T4	148985	533	0	0
T5	1365	5	0	0
T6	2087	13	0	0
T7	1717	6	0	0
T8	1809	2	0	0
T9	1850	7	0	0
T10	6404	11	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	58570	0	0
T1	763	3	0	0
T2	59018	91	0	0
T3	1979	6	0	0
T4	148985	533	0	0
T5	1365	5	0	0
T6	2087	14	0	0
T7	1717	6	0	0
T8	1809	2	0	0
T9	1850	7	0	0
T10	6404	11	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	28284	0	0
T9	1850	245	0	0
T10	6404	0	0	0
T14	294267	0	0	0
T21	1703	372	0	0
T22	17123	0	0	0
T28	0	1154	0	0
T31	0	638	0	0
T33	10104	0	0	0
T37	1515	0	0	0
T38	2886	0	0	0
T39	0	38	0	0
T40	0	284	0	0
T41	3032	0	0	0
T62	7763	0	0	0
T106	0	1209	0	0
T160	0	1036	0	0
T161	0	296	0	0
T162	0	14	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	412704	0	0
T2	59018	4147	0	0
T3	1979	0	0	0
T4	148985	1974	0	0
T5	1365	0	0	0
T6	2087	0	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	63	0	0
T10	6404	0	0	0
T14	0	3554	0	0
T20	0	3689	0	0
T21	0	47	0	0
T22	0	1311	0	0
T33	0	414	0	0
T35	0	92	0	0
T37	1515	0	0	0
T41	0	46	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	23326741	0	0
T1	763	713	0	0
T2	59018	58828	0	0
T3	1979	1576	0	0
T4	148985	144869	0	0
T5	1365	964	0	0
T6	2087	1148	0	0
T7	1717	1224	0	0
T8	1809	1676	0	0
T9	1850	1182	0	0
T10	6404	6332	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	108140	0	0
T9	1850	549	0	0
T10	6404	0	0	0
T14	294267	0	0	0
T21	1703	70	0	0
T22	17123	545	0	0
T33	10104	0	0	0
T37	1515	0	0	0
T38	2886	0	0	0
T39	0	592	0	0
T40	0	94	0	0
T41	3032	0	0	0
T62	7763	0	0	0
T96	0	878	0	0
T101	0	2201	0	0
T106	0	1362	0	0
T160	0	2756	0	0
T163	0	1203	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	4555	0	0
T3	1979	5	0	0
T4	148985	27	0	0
T5	1365	4	0	0
T6	2087	5	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	3	0	0
T10	6404	0	0	0
T11	0	1	0	0
T14	0	66	0	0
T21	1703	1	0	0
T34	0	4	0	0
T37	1515	0	0	0
T38	0	7	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	160	0	0
T17	18219	40	0	0
T18	10567	20	0	0
T19	0	20	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	1868	0	0	0
T26	30094	0	0	0
T27	15112	0	0	0
T28	5777	0	0	0
T29	2316	0	0	0
T30	7314	0	0	0
T31	3622	0	0	0
T32	5235	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	4555	0	0
T3	1979	5	0	0
T4	148985	27	0	0
T5	1365	4	0	0
T6	2087	5	0	0
T7	1717	0	0	0
T8	1809	0	0	0
T9	1850	3	0	0
T10	6404	0	0	0
T11	0	1	0	0
T14	0	66	0	0
T21	1703	1	0	0
T34	0	4	0	0
T37	1515	0	0	0
T38	0	7	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23957706	991429	0	0
T2	59018	4299	0	0
T3	1979	0	0	0
T4	148985	4427	0	0
T5	1365	0	0	0
T6	2087	99	0	0
T7	1717	22	0	0
T8	1809	6	0	0
T9	1850	42	0	0
T10	6404	0	0	0
T14	0	13161	0	0
T21	0	115	0	0
T22	0	912	0	0
T37	1515	0	0	0
T38	0	93	0	0