Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	574201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

229990

1

T1

193

T2

2169

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	433670	1			T1	407		T2	4532		T3	13
values[0x0]	184893	1			T1	229		T2	1806		T3	5
values[0x1]	185628	1			T1	223		T2	1798		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	455380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

348811

1

T1

329

T2

3424

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2546	1			T2	29		T61	2		T15	5
valid_sources[0x01]	2562	1			T2	61		T40	3		T15	20
valid_sources[0x02]	2077	1			T2	41		T6	2		T10	2
valid_sources[0x03]	2710	1			T2	5		T61	1		T65	11
valid_sources[0x04]	2696	1			T2	50		T6	2		T40	2
valid_sources[0x05]	2595	1			T2	42		T10	1		T15	5
valid_sources[0x06]	3457	1			T2	43		T9	2		T15	5
valid_sources[0x07]	2517	1			T2	42		T6	1		T9	1
valid_sources[0x08]	2855	1			T2	39		T40	5		T15	385
valid_sources[0x09]	2466	1			T2	64		T5	1		T83	6
valid_sources[0x0a]	3474	1			T2	34		T36	2		T37	9
valid_sources[0x0b]	2715	1			T2	24		T6	5		T10	4
valid_sources[0x0c]	3566	1			T2	27		T40	1		T62	4
valid_sources[0x0d]	2268	1			T2	18		T15	15		T36	1
valid_sources[0x0e]	2636	1			T2	70		T36	2		T62	2
valid_sources[0x0f]	3340	1			T2	36		T6	1		T15	5
valid_sources[0x10]	2334	1			T2	41		T65	13		T62	4
valid_sources[0x11]	3016	1			T2	27		T6	4		T40	2
valid_sources[0x12]	3255	1			T2	34		T10	2		T65	65
valid_sources[0x13]	2645	1			T2	60		T6	2		T10	1
valid_sources[0x14]	3042	1			T2	55		T6	1		T40	1
valid_sources[0x15]	2401	1			T2	39		T9	1		T10	1
valid_sources[0x16]	2370	1			T2	20		T40	2		T15	160
valid_sources[0x17]	2996	1			T2	28		T15	10		T37	6
valid_sources[0x18]	2952	1			T2	20		T6	2		T15	10
valid_sources[0x19]	3421	1			T2	29		T40	1		T15	5
valid_sources[0x1a]	2449	1			T2	8		T40	1		T15	166
valid_sources[0x1b]	2452	1			T2	17		T9	2		T40	3
valid_sources[0x1c]	2369	1			T2	50		T40	3		T15	5
valid_sources[0x1d]	2577	1			T2	30		T6	1		T9	4
valid_sources[0x1e]	3188	1			T2	2		T40	3		T15	5
valid_sources[0x1f]	2610	1			T2	26		T5	1		T6	2
valid_sources[0x20]	2476	1			T2	43		T6	1		T15	5
valid_sources[0x21]	2622	1			T2	17		T40	2		T61	2
valid_sources[0x22]	3515	1			T2	45		T40	2		T62	1
valid_sources[0x23]	2298	1			T2	37		T3	5		T40	4
valid_sources[0x24]	5195	1			T2	33		T36	2		T37	4
valid_sources[0x25]	3396	1			T2	26		T36	1		T37	8
valid_sources[0x26]	2742	1			T2	40		T37	6		T38	3
valid_sources[0x27]	2355	1			T2	34		T6	1		T61	2
valid_sources[0x28]	2518	1			T2	50		T15	15		T36	1
valid_sources[0x29]	2328	1			T2	12		T5	1		T40	1
valid_sources[0x2a]	4460	1			T2	29		T6	2		T9	1
valid_sources[0x2b]	2287	1			T2	11		T38	4		T16	25
valid_sources[0x2c]	2463	1			T2	50		T6	1		T10	1
valid_sources[0x2d]	3665	1			T2	61		T15	1416		T37	5
valid_sources[0x2e]	2513	1			T2	28		T40	5		T15	5
valid_sources[0x2f]	3546	1			T2	27		T6	3		T40	2
valid_sources[0x30]	2119	1			T2	32		T40	3		T61	1
valid_sources[0x31]	2620	1			T2	73		T3	2		T6	1
valid_sources[0x32]	2313	1			T2	22		T6	15		T65	6
valid_sources[0x33]	2329	1			T2	23		T40	5		T15	5
valid_sources[0x34]	3217	1			T2	34		T15	626		T62	1
valid_sources[0x35]	2555	1			T2	45		T40	1		T15	10
valid_sources[0x36]	3425	1			T2	32		T15	10		T36	1
valid_sources[0x37]	4487	1			T2	17		T61	1		T37	4
valid_sources[0x38]	2787	1			T2	39		T6	1		T9	4
valid_sources[0x39]	2256	1			T2	21		T9	1		T40	2
valid_sources[0x3a]	2491	1			T2	33		T10	1		T40	2
valid_sources[0x3b]	2224	1			T2	13		T9	1		T14	1
valid_sources[0x3c]	2283	1			T2	12		T40	1		T37	1
valid_sources[0x3d]	2909	1			T2	32		T6	3		T40	5
valid_sources[0x3e]	2540	1			T2	15		T15	5		T37	5
valid_sources[0x3f]	2317	1			T2	37		T6	7		T40	1
valid_sources[0x40]	4088	1			T2	20		T40	1		T37	5
valid_sources[0x41]	3050	1			T2	59		T10	2		T15	5
valid_sources[0x42]	2388	1			T2	20		T62	2		T38	6
valid_sources[0x43]	2369	1			T2	24		T61	1		T15	5
valid_sources[0x44]	2307	1			T2	27		T15	5		T62	2
valid_sources[0x45]	2561	1			T2	23		T40	1		T15	5
valid_sources[0x46]	2564	1			T2	30		T6	3		T40	3
valid_sources[0x47]	4476	1			T2	54		T9	1		T10	1
valid_sources[0x48]	2326	1			T2	39		T6	4		T40	1
valid_sources[0x49]	4429	1			T2	18		T6	1		T15	10
valid_sources[0x4a]	2377	1			T2	26		T6	4		T37	1
valid_sources[0x4b]	3293	1			T2	20		T5	1		T40	3
valid_sources[0x4c]	2556	1			T2	43		T61	1		T36	1
valid_sources[0x4d]	4530	1			T2	32		T6	1		T15	10
valid_sources[0x4e]	2325	1			T2	14		T10	2		T37	1
valid_sources[0x4f]	2418	1			T2	21		T15	10		T16	12
valid_sources[0x50]	2739	1			T2	20		T15	71		T36	1
valid_sources[0x51]	2507	1			T2	45		T36	1		T62	3
valid_sources[0x52]	2569	1			T2	42		T15	5		T62	2
valid_sources[0x53]	2531	1			T2	64		T9	1		T10	1
valid_sources[0x54]	4065	1			T2	8		T15	15		T36	2
valid_sources[0x55]	3314	1			T2	64		T6	1		T15	10
valid_sources[0x56]	2578	1			T2	34		T40	6		T15	10
valid_sources[0x57]	3341	1			T2	22		T15	10		T37	1
valid_sources[0x58]	2501	1			T2	32		T6	1		T40	1
valid_sources[0x59]	3544	1			T2	28		T6	5		T9	1
valid_sources[0x5a]	2599	1			T2	29		T40	3		T36	1
valid_sources[0x5b]	2537	1			T2	5		T61	2		T15	138
valid_sources[0x5c]	2536	1			T2	41		T5	1		T15	5
valid_sources[0x5d]	2800	1			T2	12		T6	3		T36	1
valid_sources[0x5e]	2231	1			T2	29		T6	4		T40	1
valid_sources[0x5f]	2366	1			T2	46		T6	1		T9	3
valid_sources[0x60]	4160	1			T2	40		T61	1		T15	1453
valid_sources[0x61]	2794	1			T2	40		T40	3		T15	5
valid_sources[0x62]	5222	1			T2	36		T6	1		T9	1
valid_sources[0x63]	2752	1			T2	10		T61	1		T15	10
valid_sources[0x64]	3402	1			T2	14		T15	10		T62	4
valid_sources[0x65]	2791	1			T2	25		T36	2		T62	3
valid_sources[0x66]	2319	1			T2	38		T61	1		T62	2
valid_sources[0x67]	3049	1			T2	36		T15	5		T36	1
valid_sources[0x68]	5102	1			T2	28		T5	2		T6	2
valid_sources[0x69]	2598	1			T2	58		T9	2		T40	1
valid_sources[0x6a]	2263	1			T2	20		T6	5		T9	4
valid_sources[0x6b]	3615	1			T2	39		T6	1		T40	3
valid_sources[0x6c]	3304	1			T2	47		T40	2		T61	1
valid_sources[0x6d]	3259	1			T2	17		T37	4		T38	4
valid_sources[0x6e]	2344	1			T2	40		T9	1		T10	1
valid_sources[0x6f]	2473	1			T2	31		T40	1		T15	5
valid_sources[0x70]	2662	1			T2	29		T6	2		T40	2
valid_sources[0x71]	2507	1			T2	17		T6	3		T40	2
valid_sources[0x72]	2355	1			T2	29		T6	1		T40	1
valid_sources[0x73]	2553	1			T2	25		T10	2		T40	1
valid_sources[0x74]	2521	1			T2	19		T10	2		T15	5
valid_sources[0x75]	5584	1			T2	42		T40	3		T36	1
valid_sources[0x76]	3420	1			T2	6		T37	7		T38	4
valid_sources[0x77]	2571	1			T2	23		T40	3		T15	18
valid_sources[0x78]	2878	1			T2	36		T6	1		T15	10
valid_sources[0x79]	3488	1			T2	33		T40	5		T15	316
valid_sources[0x7a]	2315	1			T2	12		T6	4		T40	3
valid_sources[0x7b]	2554	1			T2	33		T6	3		T40	2
valid_sources[0x7c]	2225	1			T2	36		T15	10		T36	1
valid_sources[0x7d]	3421	1			T2	27		T6	2		T9	1
valid_sources[0x7e]	3093	1			T2	24		T40	2		T61	1
valid_sources[0x7f]	2337	1			T2	46		T40	5		T15	1
valid_sources[0x80]	2330	1			T2	25		T5	3		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

123395

1

T1

73

T2

1181

T3

8

values[0x0]

all_enables

biggest_size

68994

1

T1

74

T2

652

T3

2

values[0x1]

all_enables

biggest_size

37601

1

T1

46

T2

336

T4

37