SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34976 | 1 | T1 | 300 | T4 | 395 | T37 | 419 | ||||
others[1] | 34915 | 1 | T1 | 310 | T4 | 426 | T37 | 403 | ||||
others[2] | 34921 | 1 | T1 | 279 | T4 | 405 | T37 | 389 | ||||
others[3] | 58661 | 1 | T1 | 512 | T4 | 645 | T37 | 660 | ||||
false | 21275 | 1 | T1 | 50 | T2 | 160 | T4 | 50 | ||||
true | 31711 | 1 | T1 | 52 | T2 | 234 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34709 | 1 | T1 | 289 | T4 | 396 | T37 | 402 | ||||
others[1] | 35116 | 1 | T1 | 305 | T4 | 411 | T37 | 393 | ||||
others[2] | 35033 | 1 | T1 | 307 | T4 | 411 | T9 | 1 | ||||
others[3] | 58640 | 1 | T1 | 499 | T4 | 660 | T37 | 666 | ||||
false | 13238 | 1 | T1 | 50 | T2 | 80 | T4 | 50 | ||||
true | 23731 | 1 | T1 | 52 | T2 | 154 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 730 | 1 | T2 | 16 | T9 | 1 | T40 | 4 | ||||
others[1] | 772 | 1 | T2 | 8 | T40 | 4 | T15 | 16 | ||||
others[2] | 677 | 1 | T2 | 3 | T40 | 6 | T15 | 15 | ||||
others[3] | 1186 | 1 | T2 | 17 | T40 | 12 | T15 | 25 | ||||
false | 14492 | 1 | T1 | 2 | T2 | 193 | T3 | 1 | ||||
true | 4324 | 1 | T2 | 75 | T5 | 1 | T9 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |