Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25804253	16337	0	0
intr_enable_rd_A	25804253	31188	0	0
reset_en_rd_A	25804253	1358	0	0
reset_en_regwen_rd_A	25804253	1033	0	0
wake_info_capture_dis_rd_A	25804253	1183	0	0
wakeup_en_rd_A	25804253	1968	0	0
wakeup_en_regwen_rd_A	25804253	1091	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	16337	0	0
T2	255015	34	0	0
T3	1328	0	0	0
T4	54052	0	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	0	0	0
T10	1995	0	0	0
T15	0	61	0	0
T16	0	10	0	0
T40	4772	0	0	0
T49	0	21	0	0
T52	0	42	0	0
T90	0	14	0	0
T135	0	61	0	0
T136	0	6	0	0
T137	0	5	0	0
T138	0	73	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	31188	0	0
T1	62533	178	0	0
T2	255015	0	0	0
T3	1328	5	0	0
T4	54052	0	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	16	0	0
T10	1995	0	0	0
T16	0	1735	0	0
T48	0	178	0	0
T61	0	20	0	0
T62	0	71	0	0
T65	0	54	0	0
T87	0	207	0	0
T89	0	23	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	1358	0	0
T12	2505	0	0	0
T13	854	0	0	0
T16	437397	2	0	0
T41	1283	0	0	0
T48	24635	0	0	0
T59	0	46	0	0
T60	0	18	0	0
T79	0	9	0	0
T85	2746	0	0	0
T86	1852	0	0	0
T87	16807	0	0	0
T88	5320	0	0	0
T109	0	473	0	0
T139	0	8	0	0
T140	0	2	0	0
T141	0	9	0	0
T142	0	9	0	0
T143	0	14	0	0
T144	1227	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	1033	0	0
T50	202333	0	0	0
T59	0	28	0	0
T60	354235	22	0	0
T79	0	11	0	0
T109	0	410	0	0
T139	0	6	0	0
T140	0	1	0	0
T141	0	6	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	0	45	0	0
T146	14277	0	0	0
T147	15558	0	0	0
T148	4793	0	0	0
T149	29050	0	0	0
T150	4840	0	0	0
T151	1638	0	0	0
T152	5800	0	0	0
T153	8471	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	1183	0	0
T50	202333	0	0	0
T59	0	56	0	0
T60	354235	18	0	0
T79	0	14	0	0
T109	0	465	0	0
T139	0	15	0	0
T140	0	17	0	0
T141	0	8	0	0
T142	0	4	0	0
T143	0	19	0	0
T145	0	32	0	0
T146	14277	0	0	0
T147	15558	0	0	0
T148	4793	0	0	0
T149	29050	0	0	0
T150	4840	0	0	0
T151	1638	0	0	0
T152	5800	0	0	0
T153	8471	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	1968	0	0
T12	2505	0	0	0
T13	854	0	0	0
T16	437397	2	0	0
T41	1283	0	0	0
T48	24635	0	0	0
T59	0	165	0	0
T60	0	25	0	0
T79	0	17	0	0
T85	2746	0	0	0
T86	1852	0	0	0
T87	16807	0	0	0
T88	5320	0	0	0
T109	0	475	0	0
T139	0	3	0	0
T140	0	7	0	0
T141	0	4	0	0
T142	0	5	0	0
T143	0	13	0	0
T144	1227	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25804253	1091	0	0
T12	2505	0	0	0
T13	854	0	0	0
T16	437397	1	0	0
T41	1283	0	0	0
T48	24635	0	0	0
T59	0	44	0	0
T60	0	16	0	0
T79	0	9	0	0
T85	2746	0	0	0
T86	1852	0	0	0
T87	16807	0	0	0
T88	5320	0	0	0
T109	0	390	0	0
T139	0	8	0	0
T140	0	11	0	0
T141	0	7	0	0
T142	0	6	0	0
T143	0	5	0	0
T144	1227	0	0	0