Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	75532977	158371	0	0
StatusRise_A	75532977	176355	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75532977	158371	0	0
T1	187599	221	0	0
T2	765045	1732	0	0
T3	3984	6	0	0
T4	162156	219	0	0
T5	2130	3	0	0
T6	12864	43	0	0
T7	3777	0	0	0
T8	2766	0	0	0
T9	14652	21	0	0
T10	5985	6	0	0
T40	0	6	0	0
T83	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75532977	176355	0	0
T1	187599	226	0	0
T2	765045	1936	0	0
T3	3984	9	0	0
T4	162156	224	0	0
T5	2130	9	0	0
T6	12864	46	0	0
T7	3777	6	0	0
T8	2766	6	0	0
T9	14652	24	0	0
T10	5985	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25177659	58816	0	0
StatusRise_A	25177659	65320	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	58816	0	0
T1	62533	89	0	0
T2	255015	635	0	0
T3	1328	2	0	0
T4	54052	86	0	0
T5	710	1	0	0
T6	4288	16	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	7	0	0
T10	1995	2	0	0
T40	0	2	0	0
T83	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	65320	0	0
T1	62533	91	0	0
T2	255015	708	0	0
T3	1328	3	0	0
T4	54052	88	0	0
T5	710	3	0	0
T6	4288	17	0	0
T7	1259	2	0	0
T8	922	2	0	0
T9	4884	8	0	0
T10	1995	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25177659	58816	0	0
StatusRise_A	25177659	65321	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	58816	0	0
T1	62533	89	0	0
T2	255015	635	0	0
T3	1328	2	0	0
T4	54052	86	0	0
T5	710	1	0	0
T6	4288	16	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	7	0	0
T10	1995	2	0	0
T40	0	2	0	0
T83	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	65321	0	0
T1	62533	91	0	0
T2	255015	709	0	0
T3	1328	3	0	0
T4	54052	88	0	0
T5	710	3	0	0
T6	4288	17	0	0
T7	1259	2	0	0
T8	922	2	0	0
T9	4884	8	0	0
T10	1995	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25177659	40739	0	0
StatusRise_A	25177659	45714	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	40739	0	0
T1	62533	43	0	0
T2	255015	462	0	0
T3	1328	2	0	0
T4	54052	47	0	0
T5	710	1	0	0
T6	4288	11	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	7	0	0
T10	1995	2	0	0
T40	0	2	0	0
T83	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	45714	0	0
T1	62533	44	0	0
T2	255015	519	0	0
T3	1328	3	0	0
T4	54052	48	0	0
T5	710	3	0	0
T6	4288	12	0	0
T7	1259	2	0	0
T8	922	2	0	0
T9	4884	8	0	0
T10	1995	2	0	0