Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25178263	5118	0	0
EscTimeoutStoppedByClReset_A	25177659	3598994	0	0
EscTimeoutTriggersReset_A	5443331	296	0	0
RomAllowActiveState_A	25177659	64904	0	0
RomAllowCheckGoodState_A	25177659	64954	0	0
RomBlockActiveState_A	25177659	27183	0	0
RomBlockCheckGoodState_A	25177659	428126	0	0
RomIntgChkDisFalse_A	25177659	24489693	0	0
RomIntgChkDisTrue_A	25177659	133976	0	0
RstreqChkEsctimeout_A	25177659	4631	0	0
RstreqChkFsmterm_A	25177659	140	0	0
RstreqChkGlbesc_A	25177659	4631	0	0
RstreqChkMainpd_A	25177659	1042912	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25178263	5118	0	0
T11	14991	55	0	0
T12	2506	39	0	0
T16	437398	0	0	0
T37	18291	0	0	0
T38	26012	0	0	0
T39	0	17	0	0
T43	2193	0	0	0
T48	24636	0	0	0
T62	6635	0	0	0
T85	2747	0	0	0
T97	0	9	0	0
T130	0	144	0	0
T144	1228	0	0	0
T154	0	30	0	0
T155	0	18	0	0
T156	0	22	0	0
T157	0	15	0	0
T158	0	10	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	3598994	0	0
T1	62533	10057	0	0
T2	255015	40921	0	0
T3	1328	26	0	0
T4	54052	8760	0	0
T5	710	53	0	0
T6	4288	915	0	0
T7	1259	35	0	0
T8	922	23	0	0
T9	4884	273	0	0
T10	1995	406	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5443331	296	0	0
T11	673	3	0	0
T12	209	3	0	0
T13	0	5	0	0
T16	81958	0	0	0
T37	7382	0	0	0
T38	5485	0	0	0
T39	0	2	0	0
T43	202	0	0	0
T48	9475	0	0	0
T62	3291	0	0	0
T85	1400	0	0	0
T97	0	5	0	0
T130	0	3	0	0
T144	389	0	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	64904	0	0
T1	62533	91	0	0
T2	255015	708	0	0
T3	1328	3	0	0
T4	54052	88	0	0
T5	710	3	0	0
T6	4288	17	0	0
T7	1259	2	0	0
T8	922	2	0	0
T9	4884	8	0	0
T10	1995	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	64954	0	0
T1	62533	91	0	0
T2	255015	708	0	0
T3	1328	3	0	0
T4	54052	88	0	0
T5	710	3	0	0
T6	4288	17	0	0
T7	1259	2	0	0
T8	922	2	0	0
T9	4884	8	0	0
T10	1995	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	27183	0	0
T9	4884	1041	0	0
T10	1995	0	0	0
T14	1569	0	0	0
T15	533505	0	0	0
T23	1122	48	0	0
T35	2638	0	0	0
T40	4772	0	0	0
T42	0	1253	0	0
T48	0	22	0	0
T61	4097	0	0	0
T65	3029	0	0	0
T83	2359	0	0	0
T98	0	463	0	0
T159	0	6	0	0
T160	0	9	0	0
T161	0	216	0	0
T162	0	147	0	0
T163	0	77	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	428126	0	0
T1	62533	4189	0	0
T2	255015	1834	0	0
T3	1328	0	0	0
T4	54052	3705	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	668	0	0
T10	1995	0	0	0
T15	0	2775	0	0
T16	0	4636	0	0
T37	0	1321	0	0
T38	0	2227	0	0
T48	0	1254	0	0
T84	0	23	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	24489693	0	0
T1	62533	61522	0	0
T2	255015	249256	0	0
T3	1328	1262	0	0
T4	54052	53884	0	0
T5	710	589	0	0
T6	4288	4229	0	0
T7	1259	1114	0	0
T8	922	782	0	0
T9	4884	2650	0	0
T10	1995	1903	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	133976	0	0
T1	62533	863	0	0
T2	255015	0	0	0
T3	1328	0	0	0
T4	54052	0	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	2178	0	0
T10	1995	0	0	0
T23	0	402	0	0
T38	0	12916	0	0
T42	0	310	0	0
T48	0	974	0	0
T95	0	951	0	0
T98	0	943	0	0
T128	0	596	0	0
T159	0	287	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	4631	0	0
T2	255015	80	0	0
T3	1328	0	0	0
T4	54052	0	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	1	0	0
T10	1995	0	0	0
T11	0	1	0	0
T14	0	4	0	0
T15	0	127	0	0
T16	0	60	0	0
T23	0	1	0	0
T35	0	6	0	0
T36	0	7	0	0
T40	4772	0	0	0
T43	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	140	0	0
T20	18860	20	0	0
T21	0	20	0	0
T22	0	40	0	0
T24	0	20	0	0
T25	0	40	0	0
T26	5447	0	0	0
T27	14739	0	0	0
T28	3048	0	0	0
T29	19131	0	0	0
T30	7348	0	0	0
T31	15863	0	0	0
T32	3589	0	0	0
T33	18182	0	0	0
T34	1616	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	4631	0	0
T2	255015	80	0	0
T3	1328	0	0	0
T4	54052	0	0	0
T5	710	0	0	0
T6	4288	0	0	0
T7	1259	0	0	0
T8	922	0	0	0
T9	4884	1	0	0
T10	1995	0	0	0
T11	0	1	0	0
T14	0	4	0	0
T15	0	127	0	0
T16	0	60	0	0
T23	0	1	0	0
T35	0	6	0	0
T36	0	7	0	0
T40	4772	0	0	0
T43	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25177659	1042912	0	0
T1	62533	8030	0	0
T2	255015	9178	0	0
T3	1328	0	0	0
T4	54052	6401	0	0
T5	710	21	0	0
T6	4288	0	0	0
T7	1259	6	0	0
T8	922	5	0	0
T9	4884	1301	0	0
T10	1995	0	0	0
T15	0	19083	0	0
T23	0	42	0	0
T35	0	102	0	0