Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	507803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

190771

1

T1

137

T2

202

T3

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	359221	1			T1	252		T2	412		T3	409
values[0x0]	169349	1			T1	15		T2	227		T3	202
values[0x1]	170004	1			T1	18		T2	225		T3	250

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	402767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

295807

1

T1

166

T2

330

T3

334

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2661	1			T1	1		T3	2		T4	11
valid_sources[0x01]	1839	1			T3	2		T4	19		T6	5
valid_sources[0x02]	2822	1			T3	3		T4	14		T6	3
valid_sources[0x03]	2278	1			T3	3		T4	12		T6	2
valid_sources[0x04]	3300	1			T1	3		T3	1		T4	7
valid_sources[0x05]	2716	1			T1	1		T2	28		T3	2
valid_sources[0x06]	2834	1			T1	2		T3	6		T4	11
valid_sources[0x07]	3315	1			T1	2		T3	7		T4	10
valid_sources[0x08]	2211	1			T1	2		T3	2		T4	6
valid_sources[0x09]	2274	1			T1	3		T3	6		T4	10
valid_sources[0x0a]	3691	1			T3	5		T4	13		T6	3
valid_sources[0x0b]	3639	1			T1	2		T3	1		T4	11
valid_sources[0x0c]	2182	1			T3	12		T4	7		T6	2
valid_sources[0x0d]	2196	1			T1	2		T3	5		T4	9
valid_sources[0x0e]	3847	1			T1	2		T3	3		T4	7
valid_sources[0x0f]	2457	1			T3	2		T4	17		T6	2
valid_sources[0x10]	1987	1			T3	4		T4	10		T6	3
valid_sources[0x11]	2609	1			T1	2		T2	7		T4	6
valid_sources[0x12]	2129	1			T1	1		T3	4		T4	7
valid_sources[0x13]	4589	1			T1	1		T3	2		T4	7
valid_sources[0x14]	2584	1			T3	4		T4	11		T6	3
valid_sources[0x15]	2198	1			T1	2		T3	3		T4	15
valid_sources[0x16]	2321	1			T1	5		T3	1		T4	15
valid_sources[0x17]	2110	1			T1	3		T3	8		T4	10
valid_sources[0x18]	2880	1			T2	42		T3	8		T4	4
valid_sources[0x19]	3073	1			T1	3		T3	1		T4	8
valid_sources[0x1a]	2182	1			T4	17		T6	5		T13	10
valid_sources[0x1b]	2297	1			T1	1		T3	2		T4	11
valid_sources[0x1c]	2284	1			T1	5		T3	9		T4	10
valid_sources[0x1d]	2280	1			T3	6		T4	8		T6	5
valid_sources[0x1e]	5744	1			T3	1		T4	5		T6	1
valid_sources[0x1f]	4676	1			T1	1		T3	6		T4	12
valid_sources[0x20]	4571	1			T3	1		T4	10		T6	3
valid_sources[0x21]	2136	1			T1	1		T3	9		T4	12
valid_sources[0x22]	3303	1			T3	2		T4	14		T6	5
valid_sources[0x23]	3621	1			T3	1		T4	12		T6	5
valid_sources[0x24]	2249	1			T3	1		T4	12		T6	3
valid_sources[0x25]	2929	1			T1	2		T3	9		T4	11
valid_sources[0x26]	2295	1			T3	1		T4	6		T6	2
valid_sources[0x27]	1957	1			T1	1		T3	4		T4	17
valid_sources[0x28]	3284	1			T1	1		T3	1		T4	7
valid_sources[0x29]	2385	1			T3	3		T4	12		T6	3
valid_sources[0x2a]	2076	1			T2	18		T3	2		T4	5
valid_sources[0x2b]	2248	1			T3	6		T4	5		T6	2
valid_sources[0x2c]	2506	1			T3	3		T4	9		T6	3
valid_sources[0x2d]	2864	1			T1	1		T3	9		T4	6
valid_sources[0x2e]	4463	1			T3	3		T4	16		T52	1
valid_sources[0x2f]	3108	1			T2	3		T3	5		T4	11
valid_sources[0x30]	2971	1			T1	2		T3	4		T4	12
valid_sources[0x31]	2236	1			T1	1		T3	4		T4	10
valid_sources[0x32]	2017	1			T3	1		T4	7		T6	5
valid_sources[0x33]	4552	1			T3	4		T4	12		T6	4
valid_sources[0x34]	2149	1			T1	2		T3	4		T4	12
valid_sources[0x35]	2473	1			T1	1		T3	3		T4	14
valid_sources[0x36]	3415	1			T1	5		T3	3		T4	10
valid_sources[0x37]	2359	1			T1	1		T3	1		T4	11
valid_sources[0x38]	2401	1			T4	17		T6	1		T52	3
valid_sources[0x39]	2782	1			T1	2		T3	8		T4	11
valid_sources[0x3a]	3149	1			T1	2		T4	8		T6	2
valid_sources[0x3b]	2982	1			T1	1		T4	12		T6	3
valid_sources[0x3c]	3056	1			T1	1		T3	7		T4	12
valid_sources[0x3d]	2305	1			T3	9		T4	9		T6	1
valid_sources[0x3e]	2329	1			T1	2		T4	12		T6	1
valid_sources[0x3f]	3193	1			T2	28		T3	2		T4	13
valid_sources[0x40]	2388	1			T3	6		T4	9		T6	6
valid_sources[0x41]	3630	1			T3	12		T4	13		T6	4
valid_sources[0x42]	2265	1			T1	1		T3	2		T4	6
valid_sources[0x43]	2059	1			T1	1		T3	2		T4	6
valid_sources[0x44]	2993	1			T1	1		T4	8		T6	5
valid_sources[0x45]	2949	1			T3	5		T4	15		T6	3
valid_sources[0x46]	2215	1			T1	3		T3	3		T4	7
valid_sources[0x47]	2051	1			T3	1		T4	10		T6	4
valid_sources[0x48]	2054	1			T3	5		T4	14		T6	3
valid_sources[0x49]	5406	1			T3	5		T4	10		T6	3
valid_sources[0x4a]	2848	1			T1	1		T2	121		T3	4
valid_sources[0x4b]	2068	1			T1	3		T3	3		T4	7
valid_sources[0x4c]	3906	1			T1	1		T3	9		T4	6
valid_sources[0x4d]	3083	1			T3	2		T4	11		T21	1
valid_sources[0x4e]	2930	1			T3	3		T4	9		T6	5
valid_sources[0x4f]	2120	1			T3	1		T4	9		T6	2
valid_sources[0x50]	2002	1			T1	2		T3	3		T4	9
valid_sources[0x51]	2141	1			T1	1		T3	8		T4	7
valid_sources[0x52]	1994	1			T1	1		T3	4		T4	13
valid_sources[0x53]	1994	1			T1	3		T3	4		T4	9
valid_sources[0x54]	3248	1			T3	8		T4	9		T6	8
valid_sources[0x55]	3392	1			T3	3		T4	6		T6	5
valid_sources[0x56]	2306	1			T3	6		T4	10		T6	3
valid_sources[0x57]	2696	1			T1	1		T3	1		T4	8
valid_sources[0x58]	3059	1			T1	1		T3	1		T4	3
valid_sources[0x59]	2537	1			T1	1		T3	7		T4	6
valid_sources[0x5a]	2574	1			T1	1		T3	2		T4	8
valid_sources[0x5b]	2221	1			T1	2		T2	9		T3	1
valid_sources[0x5c]	5142	1			T3	4		T4	6		T6	3
valid_sources[0x5d]	3075	1			T1	3		T3	1		T4	16
valid_sources[0x5e]	3011	1			T3	2		T4	10		T6	2
valid_sources[0x5f]	2139	1			T1	3		T3	1		T4	6
valid_sources[0x60]	2589	1			T1	1		T3	2		T4	5
valid_sources[0x61]	2055	1			T3	3		T4	12		T6	2
valid_sources[0x62]	4322	1			T3	3		T4	4		T6	8
valid_sources[0x63]	2297	1			T1	1		T3	4		T4	10
valid_sources[0x64]	3151	1			T1	1		T3	2		T4	11
valid_sources[0x65]	2386	1			T1	1		T3	1		T4	15
valid_sources[0x66]	2089	1			T3	4		T4	11		T6	2
valid_sources[0x67]	2118	1			T3	1		T4	7		T6	3
valid_sources[0x68]	2615	1			T1	2		T3	3		T4	7
valid_sources[0x69]	2468	1			T1	3		T3	2		T4	16
valid_sources[0x6a]	2138	1			T1	1		T3	3		T4	11
valid_sources[0x6b]	2738	1			T1	1		T4	6		T6	2
valid_sources[0x6c]	2143	1			T1	4		T3	6		T4	4
valid_sources[0x6d]	2603	1			T1	4		T3	6		T4	11
valid_sources[0x6e]	2341	1			T1	1		T4	7		T6	4
valid_sources[0x6f]	3205	1			T1	4		T3	6		T4	12
valid_sources[0x70]	2157	1			T1	1		T3	2		T4	7
valid_sources[0x71]	3281	1			T3	4		T4	11		T6	5
valid_sources[0x72]	3924	1			T1	3		T3	1		T4	11
valid_sources[0x73]	2694	1			T1	1		T3	1		T4	9
valid_sources[0x74]	3297	1			T1	1		T3	4		T4	7
valid_sources[0x75]	4285	1			T1	1		T3	3		T4	13
valid_sources[0x76]	2769	1			T3	4		T4	7		T6	2
valid_sources[0x77]	3138	1			T1	1		T3	8		T4	8
valid_sources[0x78]	3096	1			T1	1		T3	2		T4	21
valid_sources[0x79]	1926	1			T3	2		T4	9		T6	8
valid_sources[0x7a]	2114	1			T3	5		T4	4		T6	4
valid_sources[0x7b]	2980	1			T1	1		T3	2		T4	12
valid_sources[0x7c]	2225	1			T1	5		T3	4		T4	10
valid_sources[0x7d]	2636	1			T1	1		T3	5		T4	11
valid_sources[0x7e]	2243	1			T1	3		T3	4		T4	10
valid_sources[0x7f]	2435	1			T1	1		T3	5		T4	10
valid_sources[0x80]	2475	1			T3	3		T4	10		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93882

1

T1

133

T2

90

T3

77

values[0x0]

all_enables

biggest_size

62834

1

T1

3

T2

77

T3

72

values[0x1]

all_enables

biggest_size

34055

1

T1

1

T2

35

T3

45