SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34706 | 1 | T2 | 404 | T3 | 305 | T6 | 384 | ||||
others[1] | 34865 | 1 | T2 | 386 | T3 | 286 | T6 | 385 | ||||
others[2] | 34963 | 1 | T2 | 426 | T3 | 322 | T6 | 405 | ||||
others[3] | 57583 | 1 | T2 | 676 | T3 | 483 | T6 | 688 | ||||
false | 18960 | 1 | T2 | 50 | T3 | 50 | T4 | 52 | ||||
true | 28932 | 1 | T1 | 12 | T2 | 102 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34951 | 1 | T2 | 394 | T3 | 306 | T6 | 396 | ||||
others[1] | 34751 | 1 | T2 | 384 | T3 | 295 | T6 | 406 | ||||
others[2] | 34415 | 1 | T2 | 423 | T3 | 268 | T6 | 381 | ||||
others[3] | 57901 | 1 | T2 | 655 | T3 | 516 | T6 | 700 | ||||
false | 12051 | 1 | T2 | 50 | T3 | 50 | T4 | 26 | ||||
true | 22088 | 1 | T1 | 12 | T2 | 102 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 681 | 1 | T1 | 1 | T5 | 5 | T13 | 14 | ||||
others[1] | 646 | 1 | T1 | 1 | T4 | 2 | T5 | 3 | ||||
others[2] | 674 | 1 | T1 | 1 | T4 | 1 | T5 | 6 | ||||
others[3] | 1091 | 1 | T1 | 1 | T4 | 4 | T5 | 8 | ||||
false | 13353 | 1 | T1 | 21 | T2 | 2 | T3 | 1 | ||||
true | 3923 | 1 | T1 | 5 | T4 | 18 | T5 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |