Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23483316	13761	0	0
intr_enable_rd_A	23483316	37655	0	0
reset_en_rd_A	23483316	979	0	0
reset_en_regwen_rd_A	23483316	780	0	0
wake_info_capture_dis_rd_A	23483316	789	0	0
wakeup_en_rd_A	23483316	1877	0	0
wakeup_en_regwen_rd_A	23483316	852	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	13761	0	0
T4	70468	2	0	0
T5	3047	0	0	0
T6	12363	0	0	0
T7	15187	0	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T13	306040	16	0	0
T14	0	126	0	0
T29	0	8	0	0
T34	0	29	0	0
T52	4959	0	0	0
T77	1674	0	0	0
T79	0	5	0	0
T88	0	19	0	0
T135	0	18	0	0
T136	0	8	0	0
T137	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	37655	0	0
T3	54058	98	0	0
T4	70468	0	0	0
T5	3047	0	0	0
T6	12363	0	0	0
T7	15187	0	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T27	0	202	0	0
T33	0	652	0	0
T36	0	325	0	0
T52	4959	0	0	0
T77	1674	0	0	0
T100	0	19	0	0
T103	0	421	0	0
T104	0	65	0	0
T130	0	114	0	0
T138	0	48	0	0
T139	0	66	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	979	0	0
T63	0	4	0	0
T80	162614	0	0	0
T124	0	4	0	0
T140	296814	29	0	0
T141	0	3	0	0
T142	0	9	0	0
T143	0	6	0	0
T144	0	8	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	14	0	0
T148	51669	0	0	0
T149	3499	0	0	0
T150	1770	0	0	0
T151	4183	0	0	0
T152	18528	0	0	0
T153	3626	0	0	0
T154	2125	0	0	0
T155	553	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	780	0	0
T63	0	15	0	0
T80	162614	0	0	0
T124	0	8	0	0
T140	296814	14	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	14	0	0
T144	0	7	0	0
T147	0	5	0	0
T148	51669	0	0	0
T149	3499	0	0	0
T150	1770	0	0	0
T151	4183	0	0	0
T152	18528	0	0	0
T153	3626	0	0	0
T154	2125	0	0	0
T155	553	0	0	0
T156	0	1	0	0
T157	0	6	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	789	0	0
T63	0	21	0	0
T80	162614	0	0	0
T90	0	8	0	0
T124	0	6	0	0
T140	296814	14	0	0
T142	0	9	0	0
T143	0	7	0	0
T144	0	5	0	0
T145	0	3	0	0
T147	0	9	0	0
T148	51669	0	0	0
T149	3499	0	0	0
T150	1770	0	0	0
T151	4183	0	0	0
T152	18528	0	0	0
T153	3626	0	0	0
T154	2125	0	0	0
T155	553	0	0	0
T156	0	8	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	1877	0	0
T80	162614	0	0	0
T90	0	2	0	0
T140	296814	17	0	0
T141	0	18	0	0
T142	0	5	0	0
T143	0	8	0	0
T144	0	8	0	0
T145	0	3	0	0
T146	0	6	0	0
T148	51669	0	0	0
T149	3499	0	0	0
T150	1770	0	0	0
T151	4183	0	0	0
T152	18528	0	0	0
T153	3626	0	0	0
T154	2125	0	0	0
T155	553	0	0	0
T156	0	2	0	0
T157	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23483316	852	0	0
T63	0	1	0	0
T80	162614	0	0	0
T90	0	3	0	0
T124	0	4	0	0
T140	296814	23	0	0
T141	0	6	0	0
T142	0	6	0	0
T143	0	6	0	0
T145	0	8	0	0
T146	0	5	0	0
T148	51669	0	0	0
T149	3499	0	0	0
T150	1770	0	0	0
T151	4183	0	0	0
T152	18528	0	0	0
T153	3626	0	0	0
T154	2125	0	0	0
T155	553	0	0	0
T157	0	9	0	0