Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	68768775	144628	0	0
StatusRise_A	68768775	161316	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68768775	144628	0	0
T1	19983	54	0	0
T2	173832	214	0	0
T3	162174	196	0	0
T4	211404	577	0	0
T5	9141	9	0	0
T6	37089	222	0	0
T7	45561	3	0	0
T8	53037	219	0	0
T9	20889	16	0	0
T10	9081	31	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68768775	161316	0	0
T1	19983	57	0	0
T2	173832	220	0	0
T3	162174	198	0	0
T4	211404	663	0	0
T5	9141	12	0	0
T6	37089	228	0	0
T7	45561	6	0	0
T8	53037	221	0	0
T9	20889	19	0	0
T10	9081	34	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22922925	53782	0	0
StatusRise_A	22922925	59815	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	53782	0	0
T1	6661	18	0	0
T2	57944	85	0	0
T3	54058	84	0	0
T4	70468	214	0	0
T5	3047	3	0	0
T6	12363	87	0	0
T7	15187	1	0	0
T8	17679	86	0	0
T9	6963	6	0	0
T10	3027	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	59815	0	0
T1	6661	19	0	0
T2	57944	87	0	0
T3	54058	85	0	0
T4	70468	245	0	0
T5	3047	4	0	0
T6	12363	89	0	0
T7	15187	2	0	0
T8	17679	87	0	0
T9	6963	7	0	0
T10	3027	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22922925	53782	0	0
StatusRise_A	22922925	59815	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	53782	0	0
T1	6661	18	0	0
T2	57944	85	0	0
T3	54058	84	0	0
T4	70468	214	0	0
T5	3047	3	0	0
T6	12363	87	0	0
T7	15187	1	0	0
T8	17679	86	0	0
T9	6963	6	0	0
T10	3027	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	59815	0	0
T1	6661	19	0	0
T2	57944	87	0	0
T3	54058	85	0	0
T4	70468	245	0	0
T5	3047	4	0	0
T6	12363	89	0	0
T7	15187	2	0	0
T8	17679	87	0	0
T9	6963	7	0	0
T10	3027	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22922925	37064	0	0
StatusRise_A	22922925	41686	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	37064	0	0
T1	6661	18	0	0
T2	57944	44	0	0
T3	54058	28	0	0
T4	70468	149	0	0
T5	3047	3	0	0
T6	12363	48	0	0
T7	15187	1	0	0
T8	17679	47	0	0
T9	6963	4	0	0
T10	3027	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	41686	0	0
T1	6661	19	0	0
T2	57944	46	0	0
T3	54058	28	0	0
T4	70468	173	0	0
T5	3047	4	0	0
T6	12363	50	0	0
T7	15187	2	0	0
T8	17679	47	0	0
T9	6963	5	0	0
T10	3027	8	0	0