Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	22923531	5926	0	0
EscTimeoutStoppedByClReset_A	22922925	3102079	0	0
EscTimeoutTriggersReset_A	4911333	314	0	0
RomAllowActiveState_A	22922925	59416	0	0
RomAllowCheckGoodState_A	22922925	59466	0	0
RomBlockActiveState_A	22922925	27205	0	0
RomBlockCheckGoodState_A	22922925	425265	0	0
RomIntgChkDisFalse_A	22922925	22231532	0	0
RomIntgChkDisTrue_A	22922925	171933	0	0
RstreqChkEsctimeout_A	22922925	4170	0	0
RstreqChkFsmterm_A	22922925	160	0	0
RstreqChkGlbesc_A	22922925	4170	0	0
RstreqChkMainpd_A	22922925	942859	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22923531	5926	0	0
T7	15188	55	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T11	0	10	0	0
T12	0	46	0	0
T13	306040	0	0	0
T21	14453	0	0	0
T25	0	56	0	0
T30	0	30	0	0
T32	0	8	0	0
T41	2309	0	0	0
T52	4959	0	0	0
T76	912	0	0	0
T77	1674	0	0	0
T94	0	73	0	0
T158	0	26	0	0
T159	0	270	0	0
T160	0	279	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	3102079	0	0
T1	6661	308	0	0
T2	57944	10916	0	0
T3	54058	11091	0	0
T4	70468	7170	0	0
T5	3047	37	0	0
T6	12363	2070	0	0
T7	15187	10	0	0
T8	17679	2531	0	0
T9	6963	1032	0	0
T10	3027	282	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4911333	314	0	0
T7	659	3	0	0
T8	6864	0	0	0
T9	653	0	0	0
T10	2115	0	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	49843	0	0	0
T21	7892	0	0	0
T25	0	3	0	0
T30	0	2	0	0
T32	0	4	0	0
T35	0	2	0	0
T41	222	0	0	0
T52	4467	0	0	0
T76	574	0	0	0
T77	587	0	0	0
T94	0	2	0	0
T158	0	2	0	0
T161	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	59416	0	0
T1	6661	12	0	0
T2	57944	87	0	0
T3	54058	85	0	0
T4	70468	245	0	0
T5	3047	4	0	0
T6	12363	89	0	0
T7	15187	2	0	0
T8	17679	87	0	0
T9	6963	7	0	0
T10	3027	13	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	59466	0	0
T1	6661	13	0	0
T2	57944	87	0	0
T3	54058	85	0	0
T4	70468	245	0	0
T5	3047	4	0	0
T6	12363	89	0	0
T7	15187	2	0	0
T8	17679	87	0	0
T9	6963	7	0	0
T10	3027	13	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	27205	0	0
T11	845	0	0	0
T12	15131	0	0	0
T14	333227	0	0	0
T15	3383	0	0	0
T21	14452	8	0	0
T22	0	11	0	0
T37	1526	0	0	0
T45	0	1488	0	0
T56	2670	0	0	0
T78	2751	0	0	0
T97	0	11	0	0
T128	10603	0	0	0
T129	4629	0	0	0
T162	0	6	0	0
T163	0	146	0	0
T164	0	1128	0	0
T165	0	6	0	0
T166	0	76	0	0
T167	0	224	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	425265	0	0
T2	57944	4043	0	0
T3	54058	4062	0	0
T4	70468	596	0	0
T5	3047	0	0	0
T6	12363	861	0	0
T7	15187	0	0	0
T8	17679	1282	0	0
T9	6963	0	0	0
T10	3027	161	0	0
T13	0	2225	0	0
T14	0	1741	0	0
T21	0	1042	0	0
T52	4959	0	0	0
T128	0	365	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	22231532	0	0
T1	6661	5752	0	0
T2	57944	57818	0	0
T3	54058	52636	0	0
T4	70468	68364	0	0
T5	3047	2962	0	0
T6	12363	12225	0	0
T7	15187	15097	0	0
T8	17679	17618	0	0
T9	6963	6909	0	0
T10	3027	2972	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	171933	0	0
T3	54058	1331	0	0
T4	70468	0	0	0
T5	3047	0	0	0
T6	12363	0	0	0
T7	15187	0	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T21	0	188	0	0
T22	0	1128	0	0
T27	0	281	0	0
T45	0	307	0	0
T52	4959	0	0	0
T77	1674	0	0	0
T86	0	819	0	0
T163	0	32	0	0
T164	0	1315	0	0
T166	0	535	0	0
T167	0	94	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	4170	0	0
T1	6661	5	0	0
T2	57944	0	0	0
T3	54058	0	0	0
T4	70468	14	0	0
T5	3047	0	0	0
T6	12363	0	0	0
T7	15187	1	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	71	0	0
T14	0	54	0	0
T34	0	30	0	0
T37	0	4	0	0
T41	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	160	0	0
T18	24515	20	0	0
T19	0	40	0	0
T20	0	40	0	0
T23	0	20	0	0
T24	0	40	0	0
T25	15207	0	0	0
T26	1895	0	0	0
T27	22283	0	0	0
T28	1099	0	0	0
T29	310619	0	0	0
T30	14889	0	0	0
T31	2100	0	0	0
T32	1061	0	0	0
T33	71699	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	4170	0	0
T1	6661	5	0	0
T2	57944	0	0	0
T3	54058	0	0	0
T4	70468	14	0	0
T5	3047	0	0	0
T6	12363	0	0	0
T7	15187	1	0	0
T8	17679	0	0	0
T9	6963	0	0	0
T10	3027	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	71	0	0
T14	0	54	0	0
T34	0	30	0	0
T37	0	4	0	0
T41	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22922925	942859	0	0
T1	6661	144	0	0
T2	57944	4585	0	0
T3	54058	2827	0	0
T4	70468	1410	0	0
T5	3047	0	0	0
T6	12363	1436	0	0
T7	15187	0	0	0
T8	17679	2245	0	0
T9	6963	0	0	0
T10	3027	171	0	0
T13	0	11231	0	0
T14	0	13970	0	0
T21	0	1617	0	0