Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	501710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

190090

1

T1

11

T2

10

T3

215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	357940	1			T1	17		T2	7		T3	406
values[0x0]	166908	1			T1	6		T2	7		T3	193
values[0x1]	166952	1			T1	4		T2	9		T3	259

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	396875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

294925

1

T1

13

T2

14

T3

357

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3878	1			T10	27		T39	1		T16	4
valid_sources[0x01]	2673	1			T6	1		T7	1		T10	11
valid_sources[0x02]	2479	1			T10	1		T39	2		T15	1
valid_sources[0x03]	2117	1			T7	3		T10	7		T37	4
valid_sources[0x04]	1986	1			T7	2		T10	7		T40	4
valid_sources[0x05]	2173	1			T3	37		T7	1		T10	3
valid_sources[0x06]	1960	1			T40	4		T15	3		T16	13
valid_sources[0x07]	2810	1			T7	1		T39	1		T80	3
valid_sources[0x08]	2258	1			T3	5		T10	49		T37	1
valid_sources[0x09]	1970	1			T7	2		T40	17		T16	13
valid_sources[0x0a]	2357	1			T3	3		T40	1		T16	11
valid_sources[0x0b]	3162	1			T1	2		T7	2		T10	51
valid_sources[0x0c]	3148	1			T3	1		T6	1		T7	1
valid_sources[0x0d]	2180	1			T1	1		T9	2		T39	1
valid_sources[0x0e]	2321	1			T7	1		T10	124		T40	2
valid_sources[0x0f]	2342	1			T6	1		T7	1		T10	3
valid_sources[0x10]	2195	1			T3	22		T7	1		T40	16
valid_sources[0x11]	2963	1			T3	2		T7	1		T39	3
valid_sources[0x12]	2278	1			T7	1		T37	1		T39	3
valid_sources[0x13]	2240	1			T7	1		T15	5		T16	10
valid_sources[0x14]	2016	1			T6	1		T10	110		T15	1
valid_sources[0x15]	3027	1			T7	4		T10	163		T37	5
valid_sources[0x16]	3132	1			T3	1		T7	1		T10	8
valid_sources[0x17]	2425	1			T7	2		T39	1		T15	2
valid_sources[0x18]	2219	1			T3	26		T10	5		T39	1
valid_sources[0x19]	2247	1			T7	3		T15	2		T80	14
valid_sources[0x1a]	2628	1			T7	2		T10	65		T39	1
valid_sources[0x1b]	4109	1			T1	1		T7	3		T37	4
valid_sources[0x1c]	2189	1			T15	4		T16	16		T41	1
valid_sources[0x1d]	2386	1			T1	1		T10	14		T40	6
valid_sources[0x1e]	4589	1			T7	1		T10	244		T40	9
valid_sources[0x1f]	2289	1			T3	15		T7	2		T16	14
valid_sources[0x20]	3721	1			T37	3		T39	1		T40	2
valid_sources[0x21]	4445	1			T7	2		T39	4		T40	12
valid_sources[0x22]	2503	1			T6	1		T39	1		T16	16
valid_sources[0x23]	3481	1			T7	1		T37	4		T39	1
valid_sources[0x24]	2560	1			T7	2		T10	13		T37	1
valid_sources[0x25]	2260	1			T6	1		T16	18		T41	3
valid_sources[0x26]	2159	1			T3	8		T7	3		T16	16
valid_sources[0x27]	2198	1			T6	1		T37	5		T40	4
valid_sources[0x28]	2383	1			T6	1		T7	3		T10	6
valid_sources[0x29]	2917	1			T37	4		T15	1		T16	15
valid_sources[0x2a]	2364	1			T7	3		T15	2		T16	5
valid_sources[0x2b]	4094	1			T3	11		T7	4		T10	265
valid_sources[0x2c]	2616	1			T16	8		T41	1		T26	1
valid_sources[0x2d]	2084	1			T7	1		T16	16		T41	6
valid_sources[0x2e]	2270	1			T10	78		T37	3		T40	19
valid_sources[0x2f]	3321	1			T6	1		T7	1		T37	5
valid_sources[0x30]	2743	1			T3	4		T7	1		T37	3
valid_sources[0x31]	2653	1			T3	7		T7	1		T10	13
valid_sources[0x32]	2624	1			T7	2		T10	5		T16	12
valid_sources[0x33]	2125	1			T7	1		T16	16		T41	6
valid_sources[0x34]	2126	1			T7	1		T40	2		T15	1
valid_sources[0x35]	2104	1			T3	2		T7	2		T10	25
valid_sources[0x36]	2306	1			T7	1		T10	16		T15	1
valid_sources[0x37]	2367	1			T10	12		T37	4		T15	1
valid_sources[0x38]	2844	1			T3	9		T7	1		T10	97
valid_sources[0x39]	2175	1			T7	1		T10	15		T39	3
valid_sources[0x3a]	2116	1			T3	6		T7	2		T40	7
valid_sources[0x3b]	2450	1			T6	1		T40	2		T15	1
valid_sources[0x3c]	3126	1			T7	1		T9	1		T10	14
valid_sources[0x3d]	2454	1			T3	1		T7	1		T16	14
valid_sources[0x3e]	2653	1			T10	12		T39	5		T16	20
valid_sources[0x3f]	2528	1			T10	12		T40	32		T16	13
valid_sources[0x40]	2287	1			T3	26		T7	1		T40	21
valid_sources[0x41]	2022	1			T7	1		T10	27		T15	1
valid_sources[0x42]	2262	1			T3	15		T7	1		T10	26
valid_sources[0x43]	2477	1			T6	1		T16	17		T41	7
valid_sources[0x44]	2122	1			T3	3		T7	1		T39	1
valid_sources[0x45]	2254	1			T3	8		T7	1		T37	4
valid_sources[0x46]	2254	1			T6	1		T7	1		T10	13
valid_sources[0x47]	3101	1			T3	23		T7	3		T10	49
valid_sources[0x48]	2206	1			T3	13		T6	1		T10	15
valid_sources[0x49]	2150	1			T7	1		T10	24		T37	2
valid_sources[0x4a]	2252	1			T16	12		T41	9		T42	2
valid_sources[0x4b]	2125	1			T7	1		T10	25		T16	18
valid_sources[0x4c]	5023	1			T3	2		T10	25		T16	18
valid_sources[0x4d]	2987	1			T7	1		T37	1		T39	3
valid_sources[0x4e]	2065	1			T7	1		T37	1		T40	10
valid_sources[0x4f]	2968	1			T7	2		T37	1		T16	15
valid_sources[0x50]	2527	1			T44	74		T15	1		T16	9
valid_sources[0x51]	2262	1			T3	2		T6	1		T16	9
valid_sources[0x52]	4137	1			T1	4		T7	2		T9	1
valid_sources[0x53]	2041	1			T7	1		T10	1		T16	15
valid_sources[0x54]	5047	1			T10	4		T37	4		T40	11
valid_sources[0x55]	2693	1			T7	3		T16	15		T41	6
valid_sources[0x56]	2893	1			T7	1		T10	25		T15	2
valid_sources[0x57]	2501	1			T3	18		T7	2		T10	12
valid_sources[0x58]	2639	1			T7	1		T40	8		T15	3
valid_sources[0x59]	5052	1			T3	20		T15	1		T16	13
valid_sources[0x5a]	3030	1			T7	1		T10	7		T39	2
valid_sources[0x5b]	2269	1			T3	31		T10	1		T16	17
valid_sources[0x5c]	3724	1			T3	25		T7	1		T40	8
valid_sources[0x5d]	2053	1			T7	1		T37	2		T16	9
valid_sources[0x5e]	1905	1			T3	2		T6	1		T7	1
valid_sources[0x5f]	2053	1			T3	8		T37	1		T16	19
valid_sources[0x60]	2791	1			T3	12		T16	10		T41	5
valid_sources[0x61]	4401	1			T7	1		T10	27		T39	1
valid_sources[0x62]	3066	1			T7	1		T10	12		T16	6
valid_sources[0x63]	3838	1			T7	3		T37	3		T15	2
valid_sources[0x64]	2170	1			T3	11		T7	1		T37	1
valid_sources[0x65]	1918	1			T16	12		T41	1		T26	4
valid_sources[0x66]	3830	1			T39	1		T40	8		T15	1
valid_sources[0x67]	2858	1			T10	7		T37	2		T16	13
valid_sources[0x68]	2222	1			T3	1		T7	1		T10	24
valid_sources[0x69]	2222	1			T3	10		T7	2		T37	2
valid_sources[0x6a]	2519	1			T2	23		T3	26		T10	25
valid_sources[0x6b]	2175	1			T6	1		T7	1		T10	16
valid_sources[0x6c]	2384	1			T3	14		T7	1		T10	106
valid_sources[0x6d]	2038	1			T3	4		T7	1		T9	1
valid_sources[0x6e]	5420	1			T3	9		T37	2		T39	1
valid_sources[0x6f]	2149	1			T3	6		T7	2		T15	1
valid_sources[0x70]	2342	1			T3	22		T37	2		T15	1
valid_sources[0x71]	3851	1			T3	7		T39	1		T16	17
valid_sources[0x72]	2752	1			T7	1		T40	11		T16	6
valid_sources[0x73]	4272	1			T9	1		T10	68		T40	2
valid_sources[0x74]	2093	1			T7	1		T10	52		T40	12
valid_sources[0x75]	2389	1			T10	13		T37	3		T16	10
valid_sources[0x76]	3647	1			T3	1		T39	1		T16	10
valid_sources[0x77]	2188	1			T7	1		T37	1		T39	2
valid_sources[0x78]	3581	1			T3	3		T40	1		T16	9
valid_sources[0x79]	2321	1			T1	2		T7	1		T10	12
valid_sources[0x7a]	2494	1			T6	1		T10	27		T16	10
valid_sources[0x7b]	2848	1			T3	1		T7	1		T10	13
valid_sources[0x7c]	2210	1			T3	6		T7	1		T40	27
valid_sources[0x7d]	2121	1			T7	2		T15	3		T16	13
valid_sources[0x7e]	2245	1			T37	5		T39	1		T40	4
valid_sources[0x7f]	2449	1			T3	23		T10	92		T37	4
valid_sources[0x80]	3473	1			T3	2		T7	1		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93623

1

T1

6

T2

3

T3

90

values[0x0]

all_enables

biggest_size

62578

1

T1

3

T2

5

T3

71

values[0x1]

all_enables

biggest_size

33889

1

T1

2

T2

2

T3

54