SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34751 | 1 | T3 | 293 | T5 | 1 | T40 | 419 | ||||
others[1] | 34531 | 1 | T3 | 303 | T40 | 374 | T26 | 303 | ||||
others[2] | 34742 | 1 | T3 | 283 | T40 | 388 | T25 | 1 | ||||
others[3] | 57968 | 1 | T3 | 508 | T5 | 1 | T40 | 699 | ||||
false | 19077 | 1 | T3 | 50 | T5 | 1 | T10 | 184 | ||||
true | 28935 | 1 | T1 | 1 | T2 | 5 | T3 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34460 | 1 | T3 | 306 | T40 | 394 | T26 | 318 | ||||
others[1] | 34809 | 1 | T3 | 276 | T5 | 1 | T40 | 432 | ||||
others[2] | 34741 | 1 | T3 | 308 | T40 | 406 | T26 | 294 | ||||
others[3] | 57876 | 1 | T3 | 505 | T40 | 652 | T26 | 499 | ||||
false | 12116 | 1 | T3 | 50 | T5 | 2 | T10 | 92 | ||||
true | 22037 | 1 | T1 | 1 | T2 | 5 | T3 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 695 | 1 | T7 | 8 | T10 | 3 | T38 | 1 | ||||
others[1] | 680 | 1 | T5 | 1 | T7 | 6 | T8 | 1 | ||||
others[2] | 687 | 1 | T6 | 1 | T7 | 1 | T10 | 4 | ||||
others[3] | 1146 | 1 | T7 | 10 | T10 | 6 | T38 | 3 | ||||
false | 13457 | 1 | T1 | 1 | T2 | 5 | T3 | 2 | ||||
true | 4015 | 1 | T5 | 4 | T6 | 1 | T7 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |