Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24092671	14331	0	0
intr_enable_rd_A	24092671	50312	0	0
reset_en_rd_A	24092671	1703	0	0
reset_en_regwen_rd_A	24092671	1385	0	0
wake_info_capture_dis_rd_A	24092671	1462	0	0
wakeup_en_rd_A	24092671	2555	0	0
wakeup_en_regwen_rd_A	24092671	1535	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	14331	0	0
T10	253840	7	0	0
T14	7447	0	0	0
T15	2127	0	0	0
T16	71210	0	0	0
T23	0	4	0	0
T24	0	30	0	0
T37	5247	0	0	0
T38	3378	0	0	0
T39	3471	0	0	0
T40	53186	0	0	0
T44	2287	0	0	0
T52	0	4	0	0
T77	0	11	0	0
T78	0	17	0	0
T80	2471	0	0	0
T83	0	10	0	0
T136	0	22	0	0
T137	0	7	0	0
T138	0	34	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	50312	0	0
T4	2346	12	0	0
T5	2013	28	0	0
T6	870	0	0	0
T7	3036	0	0	0
T8	7427	0	0	0
T9	1627	0	0	0
T10	253840	811	0	0
T14	7447	0	0	0
T26	0	123	0	0
T37	5247	0	0	0
T38	3378	0	0	0
T41	0	161	0	0
T43	0	9	0	0
T45	0	36	0	0
T62	0	39	0	0
T80	0	5	0	0
T139	0	1	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	1703	0	0
T17	1722	0	0	0
T24	928372	3	0	0
T56	0	4	0	0
T61	0	17	0	0
T86	0	9	0	0
T87	0	5	0	0
T88	9067	0	0	0
T89	4046	0	0	0
T90	2670	0	0	0
T91	2901	0	0	0
T92	574	0	0	0
T93	1398	0	0	0
T94	3661	0	0	0
T95	2044	0	0	0
T137	0	4	0	0
T140	0	6	0	0
T141	0	3	0	0
T142	0	8	0	0
T143	0	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	1385	0	0
T17	1722	0	0	0
T24	928372	1	0	0
T56	0	7	0	0
T61	0	12	0	0
T87	0	7	0	0
T88	9067	0	0	0
T89	4046	0	0	0
T90	2670	0	0	0
T91	2901	0	0	0
T92	574	0	0	0
T93	1398	0	0	0
T94	3661	0	0	0
T95	2044	0	0	0
T137	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	0	7	0	0
T144	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	1462	0	0
T17	1722	0	0	0
T24	928372	1	0	0
T56	0	9	0	0
T61	0	3	0	0
T87	0	3	0	0
T88	9067	0	0	0
T89	4046	0	0	0
T90	2670	0	0	0
T91	2901	0	0	0
T92	574	0	0	0
T93	1398	0	0	0
T94	3661	0	0	0
T95	2044	0	0	0
T137	0	3	0	0
T140	0	1	0	0
T141	0	11	0	0
T142	0	9	0	0
T143	0	5	0	0
T145	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	2555	0	0
T17	1722	0	0	0
T24	928372	8	0	0
T56	0	9	0	0
T61	0	5	0	0
T86	0	8	0	0
T88	9067	0	0	0
T89	4046	0	0	0
T90	2670	0	0	0
T91	2901	0	0	0
T92	574	0	0	0
T93	1398	0	0	0
T94	3661	0	0	0
T95	2044	0	0	0
T137	0	6	0	0
T140	0	8	0	0
T141	0	3	0	0
T142	0	2	0	0
T144	0	5	0	0
T145	0	7	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24092671	1535	0	0
T17	1722	0	0	0
T24	928372	4	0	0
T56	0	7	0	0
T61	0	22	0	0
T86	0	13	0	0
T88	9067	0	0	0
T89	4046	0	0	0
T90	2670	0	0	0
T91	2901	0	0	0
T92	574	0	0	0
T93	1398	0	0	0
T94	3661	0	0	0
T95	2044	0	0	0
T137	0	4	0	0
T140	0	1	0	0
T141	0	12	0	0
T142	0	9	0	0
T143	0	3	0	0
T146	0	8	0	0