Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70548150	144586	0	0
StatusRise_A	70548150	161179	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70548150	144586	0	0
T1	4170	6	0	0
T2	8052	12	0	0
T3	95484	213	0	0
T4	7038	6	0	0
T5	6039	15	0	0
T6	2610	6	0	0
T7	9108	3	0	0
T8	22281	54	0	0
T9	4881	12	0	0
T10	761520	1313	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70548150	161179	0	0
T1	4170	9	0	0
T2	8052	15	0	0
T3	95484	219	0	0
T4	7038	9	0	0
T5	6039	21	0	0
T6	2610	12	0	0
T7	9108	6	0	0
T8	22281	60	0	0
T9	4881	15	0	0
T10	761520	1446	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23516050	53591	0	0
StatusRise_A	23516050	59570	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	53591	0	0
T1	1390	2	0	0
T2	2684	4	0	0
T3	31828	84	0	0
T4	2346	2	0	0
T5	2013	5	0	0
T6	870	2	0	0
T7	3036	1	0	0
T8	7427	18	0	0
T9	1627	4	0	0
T10	253840	494	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	59570	0	0
T1	1390	3	0	0
T2	2684	5	0	0
T3	31828	86	0	0
T4	2346	3	0	0
T5	2013	7	0	0
T6	870	4	0	0
T7	3036	2	0	0
T8	7427	20	0	0
T9	1627	5	0	0
T10	253840	543	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23516050	53591	0	0
StatusRise_A	23516050	59570	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	53591	0	0
T1	1390	2	0	0
T2	2684	4	0	0
T3	31828	84	0	0
T4	2346	2	0	0
T5	2013	5	0	0
T6	870	2	0	0
T7	3036	1	0	0
T8	7427	18	0	0
T9	1627	4	0	0
T10	253840	494	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	59570	0	0
T1	1390	3	0	0
T2	2684	5	0	0
T3	31828	86	0	0
T4	2346	3	0	0
T5	2013	7	0	0
T6	870	4	0	0
T7	3036	2	0	0
T8	7427	20	0	0
T9	1627	5	0	0
T10	253840	543	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23516050	37404	0	0
StatusRise_A	23516050	42039	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	37404	0	0
T1	1390	2	0	0
T2	2684	4	0	0
T3	31828	45	0	0
T4	2346	2	0	0
T5	2013	5	0	0
T6	870	2	0	0
T7	3036	1	0	0
T8	7427	18	0	0
T9	1627	4	0	0
T10	253840	325	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	42039	0	0
T1	1390	3	0	0
T2	2684	5	0	0
T3	31828	47	0	0
T4	2346	3	0	0
T5	2013	7	0	0
T6	870	4	0	0
T7	3036	2	0	0
T8	7427	20	0	0
T9	1627	5	0	0
T10	253840	360	0	0