Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23516626	5653	0	0
EscTimeoutStoppedByClReset_A	23516050	3161995	0	0
EscTimeoutTriggersReset_A	4956997	298	0	0
RomAllowActiveState_A	23516050	59195	0	0
RomAllowCheckGoodState_A	23516050	59246	0	0
RomBlockActiveState_A	23516050	29029	0	0
RomBlockCheckGoodState_A	23516050	421594	0	0
RomIntgChkDisFalse_A	23516050	22844907	0	0
RomIntgChkDisTrue_A	23516050	158304	0	0
RstreqChkEsctimeout_A	23516050	4400	0	0
RstreqChkFsmterm_A	23516050	140	0	0
RstreqChkGlbesc_A	23516050	4400	0	0
RstreqChkMainpd_A	23516050	985689	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516626	5653	0	0
T11	15020	13	0	0
T12	2355	25	0	0
T13	0	29	0	0
T25	5522	0	0	0
T26	52612	0	0	0
T42	5728	0	0	0
T43	5454	0	0	0
T48	3067	0	0	0
T62	12728	0	0	0
T93	0	18	0	0
T108	5808	0	0	0
T139	1294	0	0	0
T147	0	2	0	0
T148	0	20	0	0
T149	0	176	0	0
T150	0	12	0	0
T151	0	55	0	0
T152	0	34	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	3161995	0	0
T1	1390	12	0	0
T2	2684	130	0	0
T3	31828	4859	0	0
T4	2346	10	0	0
T5	2013	153	0	0
T6	870	72	0	0
T7	3036	15	0	0
T8	7427	313	0	0
T9	1627	78	0	0
T10	253840	38046	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4956997	298	0	0
T11	3134	4	0	0
T12	203	2	0	0
T13	0	2	0	0
T25	401	0	0	0
T26	6107	0	0	0
T42	449	0	0	0
T43	418	0	0	0
T48	290	0	0	0
T62	1482	0	0	0
T93	0	3	0	0
T108	1227	0	0	0
T139	549	0	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T153	0	2	0	0
T154	0	8	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	59195	0	0
T1	1390	3	0	0
T2	2684	5	0	0
T3	31828	86	0	0
T4	2346	3	0	0
T5	2013	7	0	0
T6	870	4	0	0
T7	3036	2	0	0
T8	7427	13	0	0
T9	1627	5	0	0
T10	253840	543	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	59246	0	0
T1	1390	3	0	0
T2	2684	5	0	0
T3	31828	86	0	0
T4	2346	3	0	0
T5	2013	7	0	0
T6	870	4	0	0
T7	3036	2	0	0
T8	7427	14	0	0
T9	1627	5	0	0
T10	253840	543	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	29029	0	0
T5	2013	225	0	0
T6	870	0	0	0
T7	3036	0	0	0
T8	7427	0	0	0
T9	1627	0	0	0
T10	253840	0	0	0
T14	7447	0	0	0
T25	0	1552	0	0
T37	5247	0	0	0
T38	3378	0	0	0
T42	0	1192	0	0
T43	0	932	0	0
T44	2287	0	0	0
T155	0	918	0	0
T156	0	26	0	0
T157	0	358	0	0
T158	0	394	0	0
T159	0	904	0	0
T160	0	287	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	421594	0	0
T3	31828	2125	0	0
T4	2346	0	0	0
T5	2013	42	0	0
T6	870	0	0	0
T7	3036	0	0	0
T8	7427	0	0	0
T9	1627	0	0	0
T10	253840	2109	0	0
T14	7447	0	0	0
T16	0	919	0	0
T25	0	1051	0	0
T26	0	4068	0	0
T37	5247	298	0	0
T39	0	184	0	0
T40	0	3952	0	0
T41	0	68	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	22844907	0	0
T1	1390	1312	0	0
T2	2684	2374	0	0
T3	31828	31427	0	0
T4	2346	2289	0	0
T5	2013	1665	0	0
T6	870	753	0	0
T7	3036	2982	0	0
T8	7427	6453	0	0
T9	1627	1271	0	0
T10	253840	250126	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	158304	0	0
T3	31828	276	0	0
T4	2346	0	0	0
T5	2013	208	0	0
T6	870	0	0	0
T7	3036	0	0	0
T8	7427	0	0	0
T9	1627	0	0	0
T10	253840	0	0	0
T14	7447	0	0	0
T25	0	321	0	0
T26	0	1525	0	0
T37	5247	0	0	0
T42	0	2213	0	0
T43	0	153	0	0
T155	0	507	0	0
T161	0	1694	0	0
T162	0	395	0	0
T163	0	748	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	4400	0	0
T5	2013	2	0	0
T6	870	1	0	0
T7	3036	0	0	0
T8	7427	7	0	0
T9	1627	0	0	0
T10	253840	30	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	7447	0	0	0
T16	0	38	0	0
T25	0	3	0	0
T37	5247	0	0	0
T38	3378	11	0	0
T42	0	2	0	0
T44	2287	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	140	0	0
T20	12677	20	0	0
T21	13284	20	0	0
T22	0	40	0	0
T27	0	20	0	0
T28	0	40	0	0
T29	7141	0	0	0
T30	2293	0	0	0
T31	2400	0	0	0
T32	9420	0	0	0
T33	5287	0	0	0
T34	540	0	0	0
T35	6285	0	0	0
T36	30190	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	4400	0	0
T5	2013	2	0	0
T6	870	1	0	0
T7	3036	0	0	0
T8	7427	7	0	0
T9	1627	0	0	0
T10	253840	30	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	7447	0	0	0
T16	0	38	0	0
T25	0	3	0	0
T37	5247	0	0	0
T38	3378	11	0	0
T42	0	2	0	0
T44	2287	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23516050	985689	0	0
T3	31828	3729	0	0
T4	2346	0	0	0
T5	2013	100	0	0
T6	870	22	0	0
T7	3036	0	0	0
T8	7427	147	0	0
T9	1627	0	0	0
T10	253840	8950	0	0
T14	7447	0	0	0
T16	0	3878	0	0
T37	5247	353	0	0
T38	0	415	0	0
T39	0	136	0	0
T40	0	4544	0	0