Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	490138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

188396

1

T1

16

T2

40

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	351609	1			T1	42		T2	94		T3	1
values[0x0]	163040	1			T1	8		T2	41		T4	36
values[0x1]	163885	1			T1	14		T2	43		T4	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	387866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

290668

1

T1

32

T2

75

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3602	1			T9	23		T24	20		T13	4
valid_sources[0x01]	2131	1			T2	2		T4	24		T9	23
valid_sources[0x02]	2111	1			T2	2		T9	16		T58	4
valid_sources[0x03]	1868	1			T9	21		T21	9		T80	2
valid_sources[0x04]	2460	1			T9	20		T21	22		T22	11
valid_sources[0x05]	2105	1			T6	1		T9	21		T24	27
valid_sources[0x06]	2338	1			T7	3		T9	12		T24	7
valid_sources[0x07]	2952	1			T9	21		T24	18		T58	3
valid_sources[0x08]	2085	1			T2	1		T9	22		T58	1
valid_sources[0x09]	2370	1			T2	1		T6	1		T9	16
valid_sources[0x0a]	2181	1			T2	1		T6	3		T9	15
valid_sources[0x0b]	2352	1			T2	3		T6	1		T7	2
valid_sources[0x0c]	2019	1			T2	1		T9	29		T58	2
valid_sources[0x0d]	2075	1			T2	1		T6	1		T7	2
valid_sources[0x0e]	2969	1			T1	1		T9	19		T58	7
valid_sources[0x0f]	2098	1			T2	2		T6	1		T9	20
valid_sources[0x10]	4531	1			T9	21		T24	2		T22	14
valid_sources[0x11]	2412	1			T2	3		T6	3		T9	20
valid_sources[0x12]	1988	1			T1	3		T9	20		T24	9
valid_sources[0x13]	2092	1			T2	3		T6	1		T7	3
valid_sources[0x14]	2598	1			T6	3		T9	13		T62	1
valid_sources[0x15]	2568	1			T1	1		T7	1		T9	20
valid_sources[0x16]	5061	1			T6	2		T7	7		T9	21
valid_sources[0x17]	2294	1			T9	16		T58	2		T80	1
valid_sources[0x18]	2449	1			T7	1		T9	26		T24	13
valid_sources[0x19]	2188	1			T6	1		T9	18		T24	6
valid_sources[0x1a]	2041	1			T7	1		T9	25		T22	15
valid_sources[0x1b]	2222	1			T2	1		T9	23		T24	10
valid_sources[0x1c]	2235	1			T4	9		T7	1		T9	18
valid_sources[0x1d]	2238	1			T9	25		T24	4		T58	3
valid_sources[0x1e]	7143	1			T7	1		T9	34		T58	2
valid_sources[0x1f]	2576	1			T2	2		T9	15		T58	3
valid_sources[0x20]	3196	1			T1	2		T2	1		T6	3
valid_sources[0x21]	3660	1			T1	5		T2	1		T9	31
valid_sources[0x22]	2071	1			T2	1		T6	1		T7	2
valid_sources[0x23]	4546	1			T6	1		T9	16		T80	1
valid_sources[0x24]	3412	1			T2	1		T9	16		T80	1
valid_sources[0x25]	3137	1			T2	2		T9	12		T24	1
valid_sources[0x26]	2676	1			T9	25		T80	2		T14	1
valid_sources[0x27]	2113	1			T6	1		T9	24		T58	3
valid_sources[0x28]	2972	1			T2	1		T7	1		T9	26
valid_sources[0x29]	2228	1			T6	5		T7	3		T9	22
valid_sources[0x2a]	2355	1			T6	1		T9	17		T13	1
valid_sources[0x2b]	2012	1			T1	1		T6	2		T7	1
valid_sources[0x2c]	2442	1			T6	2		T7	2		T9	30
valid_sources[0x2d]	2494	1			T2	1		T7	3		T9	26
valid_sources[0x2e]	2728	1			T6	1		T9	24		T58	1
valid_sources[0x2f]	2832	1			T6	2		T7	4		T9	27
valid_sources[0x30]	2310	1			T2	1		T7	1		T9	18
valid_sources[0x31]	3081	1			T2	1		T5	26		T7	2
valid_sources[0x32]	3190	1			T7	4		T9	16		T24	9
valid_sources[0x33]	2403	1			T1	1		T9	24		T22	12
valid_sources[0x34]	3274	1			T2	1		T9	25		T58	4
valid_sources[0x35]	2605	1			T6	2		T7	1		T9	20
valid_sources[0x36]	1983	1			T2	1		T9	16		T24	19
valid_sources[0x37]	2177	1			T2	2		T7	3		T9	18
valid_sources[0x38]	2469	1			T2	1		T6	1		T7	3
valid_sources[0x39]	2599	1			T4	9		T6	1		T7	2
valid_sources[0x3a]	2091	1			T6	2		T9	23		T21	7
valid_sources[0x3b]	2049	1			T1	6		T2	1		T6	3
valid_sources[0x3c]	2920	1			T2	1		T6	3		T7	4
valid_sources[0x3d]	2222	1			T4	5		T7	1		T9	25
valid_sources[0x3e]	2177	1			T6	2		T9	16		T24	21
valid_sources[0x3f]	2098	1			T6	1		T9	15		T80	2
valid_sources[0x40]	1955	1			T2	1		T9	17		T23	3
valid_sources[0x41]	1932	1			T2	1		T7	1		T9	20
valid_sources[0x42]	2952	1			T2	2		T6	1		T9	23
valid_sources[0x43]	2937	1			T1	4		T2	2		T7	3
valid_sources[0x44]	2108	1			T7	4		T9	25		T21	5
valid_sources[0x45]	3428	1			T6	1		T9	20		T24	5
valid_sources[0x46]	3604	1			T2	3		T6	1		T9	16
valid_sources[0x47]	2804	1			T2	1		T6	1		T7	1
valid_sources[0x48]	3132	1			T1	1		T2	1		T7	1
valid_sources[0x49]	2235	1			T2	2		T4	14		T9	10
valid_sources[0x4a]	2051	1			T2	1		T7	1		T9	18
valid_sources[0x4b]	2064	1			T7	1		T9	16		T22	8
valid_sources[0x4c]	3532	1			T1	1		T4	2		T7	7
valid_sources[0x4d]	2258	1			T9	23		T81	1		T62	1
valid_sources[0x4e]	2105	1			T1	1		T6	1		T9	23
valid_sources[0x4f]	2710	1			T2	1		T9	19		T24	14
valid_sources[0x50]	2467	1			T9	19		T21	6		T81	1
valid_sources[0x51]	2082	1			T2	1		T9	18		T24	24
valid_sources[0x52]	3929	1			T2	1		T6	2		T9	17
valid_sources[0x53]	1959	1			T1	1		T7	1		T9	19
valid_sources[0x54]	2554	1			T2	1		T7	1		T9	12
valid_sources[0x55]	1772	1			T2	1		T6	1		T9	15
valid_sources[0x56]	2103	1			T6	1		T9	19		T24	5
valid_sources[0x57]	2371	1			T2	1		T6	3		T7	2
valid_sources[0x58]	2110	1			T2	1		T7	1		T9	22
valid_sources[0x59]	2994	1			T9	16		T21	8		T14	11
valid_sources[0x5a]	3089	1			T2	2		T6	2		T9	14
valid_sources[0x5b]	3765	1			T6	5		T9	30		T62	2
valid_sources[0x5c]	3435	1			T2	3		T6	2		T7	2
valid_sources[0x5d]	2254	1			T2	4		T9	16		T22	12
valid_sources[0x5e]	2303	1			T6	3		T9	22		T58	1
valid_sources[0x5f]	2543	1			T7	3		T9	19		T24	13
valid_sources[0x60]	4288	1			T7	2		T9	25		T58	4
valid_sources[0x61]	2121	1			T7	1		T9	17		T58	4
valid_sources[0x62]	2194	1			T9	22		T58	1		T80	3
valid_sources[0x63]	2654	1			T2	2		T7	2		T9	23
valid_sources[0x64]	1994	1			T2	3		T4	1		T9	27
valid_sources[0x65]	2521	1			T1	1		T9	22		T24	13
valid_sources[0x66]	3516	1			T6	2		T9	15		T58	1
valid_sources[0x67]	3703	1			T2	1		T9	24		T58	1
valid_sources[0x68]	2452	1			T7	1		T9	21		T24	1
valid_sources[0x69]	2266	1			T6	12		T7	1		T9	21
valid_sources[0x6a]	2736	1			T2	1		T4	23		T7	1
valid_sources[0x6b]	3705	1			T1	1		T6	1		T9	17
valid_sources[0x6c]	3269	1			T7	1		T9	12		T58	1
valid_sources[0x6d]	2271	1			T1	1		T9	19		T24	14
valid_sources[0x6e]	2167	1			T9	19		T58	5		T21	2
valid_sources[0x6f]	2290	1			T2	2		T6	8		T9	15
valid_sources[0x70]	2853	1			T2	1		T9	22		T58	2
valid_sources[0x71]	2058	1			T2	2		T6	1		T9	17
valid_sources[0x72]	2134	1			T2	1		T9	18		T58	3
valid_sources[0x73]	2381	1			T2	2		T7	1		T9	21
valid_sources[0x74]	1985	1			T2	1		T4	13		T6	3
valid_sources[0x75]	3130	1			T2	1		T6	1		T7	3
valid_sources[0x76]	2929	1			T9	19		T58	5		T21	8
valid_sources[0x77]	2208	1			T2	2		T6	2		T7	1
valid_sources[0x78]	2959	1			T2	3		T6	1		T7	1
valid_sources[0x79]	1904	1			T2	1		T9	26		T58	4
valid_sources[0x7a]	2116	1			T1	3		T7	1		T9	22
valid_sources[0x7b]	2126	1			T6	1		T9	25		T14	11
valid_sources[0x7c]	3250	1			T2	1		T6	1		T7	4
valid_sources[0x7d]	2073	1			T2	3		T9	27		T21	11
valid_sources[0x7e]	2108	1			T2	1		T9	21		T22	13
valid_sources[0x7f]	2369	1			T6	1		T7	2		T9	22
valid_sources[0x80]	3124	1			T9	8		T24	14		T21	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93138

1

T1

9

T2

16

T3

1

values[0x0]

all_enables

biggest_size

61472

1

T1

3

T2

19

T4

13

values[0x1]

all_enables

biggest_size

33786

1

T1

4

T2

5

T4

3