SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34965 | 1 | T24 | 383 | T21 | 304 | T37 | 329 | ||||
others[1] | 35271 | 1 | T24 | 416 | T21 | 303 | T37 | 301 | ||||
others[2] | 35002 | 1 | T1 | 1 | T24 | 387 | T21 | 280 | ||||
others[3] | 58027 | 1 | T1 | 1 | T24 | 676 | T21 | 501 | ||||
false | 18333 | 1 | T1 | 1 | T9 | 130 | T24 | 50 | ||||
true | 28210 | 1 | T1 | 4 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35082 | 1 | T24 | 395 | T21 | 284 | T37 | 310 | ||||
others[1] | 35157 | 1 | T1 | 1 | T24 | 420 | T21 | 300 | ||||
others[2] | 34797 | 1 | T24 | 405 | T21 | 304 | T37 | 326 | ||||
others[3] | 58367 | 1 | T24 | 666 | T21 | 522 | T37 | 468 | ||||
false | 11759 | 1 | T1 | 3 | T9 | 65 | T24 | 50 | ||||
true | 21703 | 1 | T1 | 6 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 659 | 1 | T4 | 9 | T6 | 3 | T7 | 1 | ||||
others[1] | 630 | 1 | T4 | 3 | T6 | 7 | T9 | 3 | ||||
others[2] | 667 | 1 | T1 | 1 | T4 | 5 | T6 | 5 | ||||
others[3] | 1099 | 1 | T4 | 9 | T6 | 9 | T7 | 4 | ||||
false | 13178 | 1 | T1 | 4 | T2 | 1 | T3 | 1 | ||||
true | 3864 | 1 | T1 | 1 | T4 | 1 | T7 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |