Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T21,T44

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23338868	6002	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23338868	249157	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23338868	9655459	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23338868	249166	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23338868	6002	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23338868	249157	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23338868	9655459	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23338868	249166	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	6002	0	0
T5	1294	1	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	41	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	17	0	0
T21	0	27	0	0
T22	0	21	0	0
T23	1790	0	0	0
T24	21147	21	0	0
T37	0	24	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	5120	0	0	0
T78	0	20	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	249157	0	0
T5	1294	9	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	996	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	281	0	0
T21	0	630	0	0
T22	0	1002	0	0
T23	1790	0	0	0
T24	21147	406	0	0
T37	0	407	0	0
T44	0	195	0	0
T45	0	437	0	0
T58	5120	0	0	0
T78	0	1277	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	9655459	0	0
T2	5342	2332	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	1026	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	8540	0	0
T9	128755	51032	0	0
T10	2480	1605	0	0
T13	0	1189	0	0
T21	0	14528	0	0
T24	21147	11114	0	0
T44	0	131	0	0
T58	0	2343	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	249166	0	0
T5	1294	9	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	996	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	281	0	0
T21	0	632	0	0
T22	0	1005	0	0
T23	1790	0	0	0
T24	21147	406	0	0
T37	0	407	0	0
T44	0	195	0	0
T45	0	437	0	0
T58	5120	0	0	0
T78	0	1277	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	6002	0	0
T5	1294	1	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	41	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	17	0	0
T21	0	27	0	0
T22	0	21	0	0
T23	1790	0	0	0
T24	21147	21	0	0
T37	0	24	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	5120	0	0	0
T78	0	20	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	249157	0	0
T5	1294	9	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	996	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	281	0	0
T21	0	630	0	0
T22	0	1002	0	0
T23	1790	0	0	0
T24	21147	406	0	0
T37	0	407	0	0
T44	0	195	0	0
T45	0	437	0	0
T58	5120	0	0	0
T78	0	1277	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	9655459	0	0
T2	5342	2332	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	1026	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	8540	0	0
T9	128755	51032	0	0
T10	2480	1605	0	0
T13	0	1189	0	0
T21	0	14528	0	0
T24	21147	11114	0	0
T44	0	131	0	0
T58	0	2343	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	249166	0	0
T5	1294	9	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	996	0	0
T10	2480	0	0	0
T13	2109	0	0	0
T14	0	281	0	0
T21	0	632	0	0
T22	0	1005	0	0
T23	1790	0	0	0
T24	21147	406	0	0
T37	0	407	0	0
T44	0	195	0	0
T45	0	437	0	0
T58	5120	0	0	0
T78	0	1277	0	0