Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23917807	15307	0	0
intr_enable_rd_A	23917807	39895	0	0
reset_en_rd_A	23917807	1108	0	0
reset_en_regwen_rd_A	23917807	919	0	0
wake_info_capture_dis_rd_A	23917807	920	0	0
wakeup_en_rd_A	23917807	1800	0	0
wakeup_en_regwen_rd_A	23917807	937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	15307	0	0
T9	128755	6	0	0
T10	2480	0	0	0
T11	15088	0	0	0
T13	2109	0	0	0
T14	0	1	0	0
T21	23455	0	0	0
T22	0	8	0	0
T23	1790	0	0	0
T24	21147	0	0	0
T29	0	10	0	0
T36	1584	0	0	0
T43	3059	0	0	0
T51	0	17	0	0
T58	5120	0	0	0
T82	0	51	0	0
T83	0	106	0	0
T95	0	13	0	0
T149	0	1	0	0
T150	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	39895	0	0
T11	15088	0	0	0
T12	15513	0	0	0
T14	53251	379	0	0
T21	23455	189	0	0
T22	0	444	0	0
T36	1584	0	0	0
T39	2107	0	0	0
T43	3059	0	0	0
T44	1422	0	0	0
T59	0	28	0	0
T79	1571	0	0	0
T80	10445	0	0	0
T81	0	4	0	0
T95	0	2393	0	0
T151	0	23	0	0
T152	0	45	0	0
T153	0	92	0	0
T154	0	17	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	1108	0	0
T14	53251	7	0	0
T22	115286	0	0	0
T37	16696	0	0	0
T40	828	0	0	0
T45	3202	0	0	0
T50	0	9	0	0
T62	13576	0	0	0
T81	2295	0	0	0
T121	0	4	0	0
T151	2755	0	0	0
T155	0	1	0	0
T156	0	9	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	8	0	0
T161	0	9	0	0
T162	3302	0	0	0
T163	2513	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	919	0	0
T22	115286	4	0	0
T37	16696	0	0	0
T38	5918	0	0	0
T40	828	0	0	0
T41	3951	0	0	0
T45	3202	0	0	0
T50	0	8	0	0
T55	0	30	0	0
T59	10133	0	0	0
T121	0	14	0	0
T136	0	8	0	0
T151	2755	0	0	0
T155	0	1	0	0
T157	0	5	0	0
T159	0	9	0	0
T160	0	8	0	0
T161	0	5	0	0
T162	3302	0	0	0
T163	2513	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	920	0	0
T14	53251	10	0	0
T22	115286	0	0	0
T37	16696	0	0	0
T40	828	0	0	0
T45	3202	0	0	0
T50	0	6	0	0
T62	13576	0	0	0
T81	2295	0	0	0
T121	0	10	0	0
T136	0	5	0	0
T151	2755	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	13	0	0
T160	0	10	0	0
T161	0	1	0	0
T162	3302	0	0	0
T163	2513	0	0	0
T164	0	6	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	1800	0	0
T14	53251	8	0	0
T22	115286	1	0	0
T37	16696	0	0	0
T40	828	0	0	0
T45	3202	0	0	0
T62	13576	0	0	0
T81	2295	0	0	0
T151	2755	0	0	0
T155	0	9	0	0
T156	0	8	0	0
T157	0	8	0	0
T158	0	1	0	0
T159	0	10	0	0
T160	0	4	0	0
T161	0	7	0	0
T162	3302	0	0	0
T163	2513	0	0	0
T164	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23917807	937	0	0
T14	53251	8	0	0
T22	115286	0	0	0
T37	16696	0	0	0
T40	828	0	0	0
T45	3202	0	0	0
T50	0	9	0	0
T62	13576	0	0	0
T81	2295	0	0	0
T95	0	1	0	0
T151	2755	0	0	0
T155	0	4	0	0
T156	0	7	0	0
T157	0	9	0	0
T159	0	9	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	3302	0	0	0
T163	2513	0	0	0
T164	0	5	0	0