Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70016604	139354	0	0
StatusRise_A	70016604	155721	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70016604	139354	0	0
T1	17877	24	0	0
T2	16026	35	0	0
T3	46272	3	0	0
T4	4845	3	0	0
T5	3882	6	0	0
T6	4698	0	0	0
T7	8436	54	0	0
T8	47601	43	0	0
T9	386265	1198	0	0
T10	7440	14	0	0
T24	0	207	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70016604	155721	0	0
T1	17877	30	0	0
T2	16026	37	0	0
T3	46272	6	0	0
T4	4845	6	0	0
T5	3882	9	0	0
T6	4698	3	0	0
T7	8436	57	0	0
T8	47601	46	0	0
T9	386265	1366	0	0
T10	7440	16	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23338868	51613	0	0
StatusRise_A	23338868	57510	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	51613	0	0
T1	5959	8	0	0
T2	5342	13	0	0
T3	15424	1	0	0
T4	1615	1	0	0
T5	1294	2	0	0
T6	1566	0	0	0
T7	2812	18	0	0
T8	15867	17	0	0
T9	128755	428	0	0
T10	2480	5	0	0
T24	0	80	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	57510	0	0
T1	5959	10	0	0
T2	5342	14	0	0
T3	15424	2	0	0
T4	1615	2	0	0
T5	1294	3	0	0
T6	1566	1	0	0
T7	2812	19	0	0
T8	15867	18	0	0
T9	128755	489	0	0
T10	2480	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23338868	51613	0	0
StatusRise_A	23338868	57510	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	51613	0	0
T1	5959	8	0	0
T2	5342	13	0	0
T3	15424	1	0	0
T4	1615	1	0	0
T5	1294	2	0	0
T6	1566	0	0	0
T7	2812	18	0	0
T8	15867	17	0	0
T9	128755	428	0	0
T10	2480	5	0	0
T24	0	80	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	57510	0	0
T1	5959	10	0	0
T2	5342	14	0	0
T3	15424	2	0	0
T4	1615	2	0	0
T5	1294	3	0	0
T6	1566	1	0	0
T7	2812	19	0	0
T8	15867	18	0	0
T9	128755	489	0	0
T10	2480	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23338868	36128	0	0
StatusRise_A	23338868	40701	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	36128	0	0
T1	5959	8	0	0
T2	5342	9	0	0
T3	15424	1	0	0
T4	1615	1	0	0
T5	1294	2	0	0
T6	1566	0	0	0
T7	2812	18	0	0
T8	15867	9	0	0
T9	128755	342	0	0
T10	2480	4	0	0
T24	0	47	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	40701	0	0
T1	5959	10	0	0
T2	5342	9	0	0
T3	15424	2	0	0
T4	1615	2	0	0
T5	1294	3	0	0
T6	1566	1	0	0
T7	2812	19	0	0
T8	15867	10	0	0
T9	128755	388	0	0
T10	2480	4	0	0