Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23339460	5065	0	0
EscTimeoutStoppedByClReset_A	23338868	3221303	0	0
EscTimeoutTriggersReset_A	5103899	299	0	0
RomAllowActiveState_A	23338868	57113	0	0
RomAllowCheckGoodState_A	23338868	57164	0	0
RomBlockActiveState_A	23338868	35205	0	0
RomBlockCheckGoodState_A	23338868	435705	0	0
RomIntgChkDisFalse_A	23338868	22689216	0	0
RomIntgChkDisTrue_A	23338868	141470	0	0
RstreqChkEsctimeout_A	23338868	4170	0	0
RstreqChkFsmterm_A	23338868	160	0	0
RstreqChkGlbesc_A	23338868	4170	0	0
RstreqChkMainpd_A	23338868	958252	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23339460	5065	0	0
T3	15424	92	0	0
T4	1615	0	0	0
T5	1295	0	0	0
T6	1566	0	0	0
T7	2813	0	0	0
T8	15868	0	0	0
T9	128756	0	0	0
T10	2481	0	0	0
T11	0	31	0	0
T12	0	271	0	0
T24	21147	0	0	0
T39	0	31	0	0
T40	0	8	0	0
T58	5121	0	0	0
T163	0	24	0	0
T165	0	167	0	0
T166	0	11	0	0
T167	0	20	0	0
T168	0	141	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	3221303	0	0
T1	5959	461	0	0
T2	5342	592	0	0
T3	15424	14	0	0
T4	1615	12	0	0
T5	1294	19	0	0
T6	1566	0	0	0
T7	2812	443	0	0
T8	15867	2855	0	0
T9	128755	13207	0	0
T10	2480	203	0	0
T24	0	2639	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5103899	299	0	0
T3	363	3	0	0
T4	963	0	0	0
T5	414	0	0	0
T6	1591	0	0	0
T7	802	0	0	0
T8	1618	0	0	0
T9	44790	0	0	0
T10	1098	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T24	8383	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T58	2197	0	0	0
T163	0	2	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	2	0	0
T169	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	57113	0	0
T1	5959	10	0	0
T2	5342	14	0	0
T3	15424	2	0	0
T4	1615	2	0	0
T5	1294	3	0	0
T6	1566	1	0	0
T7	2812	19	0	0
T8	15867	18	0	0
T9	128755	489	0	0
T10	2480	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	57164	0	0
T1	5959	10	0	0
T2	5342	14	0	0
T3	15424	2	0	0
T4	1615	2	0	0
T5	1294	3	0	0
T6	1566	1	0	0
T7	2812	19	0	0
T8	15867	18	0	0
T9	128755	489	0	0
T10	2480	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	35205	0	0
T1	5959	1144	0	0
T2	5342	0	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	0	0	0
T10	2480	0	0	0
T21	0	2	0	0
T23	0	318	0	0
T36	0	14	0	0
T37	0	6	0	0
T38	0	1232	0	0
T153	0	6	0	0
T170	0	894	0	0
T171	0	16	0	0
T172	0	734	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	435705	0	0
T1	5959	785	0	0
T2	5342	0	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	1493	0	0
T10	2480	0	0	0
T14	0	644	0	0
T21	0	1303	0	0
T22	0	893	0	0
T23	0	85	0	0
T24	0	1274	0	0
T37	0	922	0	0
T38	0	1080	0	0
T78	0	4065	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	22689216	0	0
T1	5959	5540	0	0
T2	5342	5255	0	0
T3	15424	15327	0	0
T4	1615	1518	0	0
T5	1294	1222	0	0
T6	1566	1474	0	0
T7	2812	2736	0	0
T8	15867	15776	0	0
T9	128755	124337	0	0
T10	2480	2427	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	141470	0	0
T1	5959	256	0	0
T2	5342	0	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	0	0	0
T8	15867	0	0	0
T9	128755	0	0	0
T10	2480	0	0	0
T21	0	541	0	0
T23	0	820	0	0
T36	0	120	0	0
T37	0	493	0	0
T38	0	2164	0	0
T78	0	18754	0	0
T170	0	1837	0	0
T171	0	357	0	0
T172	0	95	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	4170	0	0
T1	5959	3	0	0
T2	5342	0	0	0
T3	15424	1	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	10	0	0
T8	15867	0	0	0
T9	128755	39	0	0
T10	2480	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T23	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T43	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	160	0	0
T18	46322	40	0	0
T19	0	20	0	0
T20	0	20	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	7510	0	0	0
T28	15341	0	0	0
T29	277713	0	0	0
T30	17770	0	0	0
T31	615	0	0	0
T32	3823	0	0	0
T33	2175	0	0	0
T34	2639	0	0	0
T35	19381	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	4170	0	0
T1	5959	3	0	0
T2	5342	0	0	0
T3	15424	1	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	10	0	0
T8	15867	0	0	0
T9	128755	39	0	0
T10	2480	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T23	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T43	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23338868	958252	0	0
T1	5959	1415	0	0
T2	5342	0	0	0
T3	15424	0	0	0
T4	1615	0	0	0
T5	1294	0	0	0
T6	1566	0	0	0
T7	2812	288	0	0
T8	15867	0	0	0
T9	128755	3958	0	0
T10	2480	0	0	0
T14	0	741	0	0
T21	0	1810	0	0
T22	0	1735	0	0
T23	0	24	0	0
T24	0	1119	0	0
T36	0	46	0	0
T37	0	1046	0	0