Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	544116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207173

1

T1

16

T2

196

T3

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	390130	1			T1	44		T2	421		T3	109
values[0x0]	180134	1			T1	11		T2	227		T3	73
values[0x1]	181025	1			T1	11		T2	225		T3	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	430969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

320320

1

T1

29

T2

344

T3

93

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3404	1			T3	17		T4	2		T5	1
valid_sources[0x01]	2294	1			T7	1		T8	5		T9	1
valid_sources[0x02]	2351	1			T5	1		T7	15		T8	8
valid_sources[0x03]	2481	1			T5	1		T8	1		T10	4
valid_sources[0x04]	3003	1			T5	1		T7	2		T8	4
valid_sources[0x05]	4004	1			T5	1		T7	8		T8	3
valid_sources[0x06]	2400	1			T6	11		T7	5		T8	2
valid_sources[0x07]	4314	1			T7	5		T8	3		T9	1
valid_sources[0x08]	2992	1			T4	12		T5	1		T8	1
valid_sources[0x09]	2596	1			T7	9		T8	3		T35	2
valid_sources[0x0a]	2328	1			T7	4		T8	4		T9	4
valid_sources[0x0b]	3567	1			T5	1		T6	7		T8	7
valid_sources[0x0c]	3892	1			T5	2		T6	23		T8	6
valid_sources[0x0d]	4160	1			T5	1		T7	12		T8	3
valid_sources[0x0e]	2757	1			T7	10		T8	4		T9	2
valid_sources[0x0f]	2263	1			T6	12		T7	8		T8	3
valid_sources[0x10]	3062	1			T3	3		T5	1		T6	8
valid_sources[0x11]	2149	1			T5	1		T7	13		T8	4
valid_sources[0x12]	2314	1			T5	1		T6	1		T7	9
valid_sources[0x13]	3277	1			T6	24		T7	8		T8	4
valid_sources[0x14]	3222	1			T5	1		T7	11		T8	3
valid_sources[0x15]	3641	1			T5	1		T6	12		T7	4
valid_sources[0x16]	3226	1			T7	9		T8	3		T9	1
valid_sources[0x17]	3270	1			T5	1		T7	10		T8	2
valid_sources[0x18]	3321	1			T6	12		T7	3		T8	5
valid_sources[0x19]	2952	1			T6	21		T7	6		T8	4
valid_sources[0x1a]	2372	1			T8	5		T9	3		T35	2
valid_sources[0x1b]	3602	1			T6	202		T7	12		T8	1
valid_sources[0x1c]	2185	1			T6	7		T7	6		T8	2
valid_sources[0x1d]	2478	1			T8	3		T9	2		T35	1
valid_sources[0x1e]	2311	1			T5	1		T6	22		T7	11
valid_sources[0x1f]	2297	1			T6	24		T7	4		T8	4
valid_sources[0x20]	3635	1			T7	7		T8	1		T9	5
valid_sources[0x21]	2598	1			T5	1		T6	26		T7	8
valid_sources[0x22]	2526	1			T6	23		T7	3		T8	2
valid_sources[0x23]	2419	1			T6	12		T7	3		T8	4
valid_sources[0x24]	2717	1			T6	11		T7	4		T8	5
valid_sources[0x25]	2322	1			T6	12		T8	3		T9	1
valid_sources[0x26]	3363	1			T6	11		T7	5		T8	3
valid_sources[0x27]	2616	1			T6	23		T7	5		T8	2
valid_sources[0x28]	2274	1			T6	22		T7	12		T8	5
valid_sources[0x29]	3222	1			T5	1		T7	5		T8	2
valid_sources[0x2a]	3572	1			T7	3		T8	1		T9	2
valid_sources[0x2b]	2631	1			T6	11		T7	6		T8	4
valid_sources[0x2c]	2824	1			T7	12		T8	4		T9	5
valid_sources[0x2d]	2214	1			T7	2		T8	5		T14	1
valid_sources[0x2e]	5270	1			T7	3		T8	2		T9	1
valid_sources[0x2f]	5847	1			T6	11		T7	2		T8	2
valid_sources[0x30]	2793	1			T4	1		T6	11		T7	6
valid_sources[0x31]	3050	1			T7	5		T8	3		T9	1
valid_sources[0x32]	2740	1			T7	6		T8	3		T35	3
valid_sources[0x33]	2621	1			T7	3		T8	3		T35	3
valid_sources[0x34]	2357	1			T5	1		T6	35		T7	8
valid_sources[0x35]	2453	1			T3	71		T5	2		T7	2
valid_sources[0x36]	2896	1			T5	2		T6	11		T7	10
valid_sources[0x37]	2875	1			T7	1		T8	3		T35	4
valid_sources[0x38]	2336	1			T5	1		T7	2		T8	5
valid_sources[0x39]	3114	1			T5	1		T7	2		T9	2
valid_sources[0x3a]	2497	1			T7	7		T8	3		T35	3
valid_sources[0x3b]	2483	1			T5	2		T6	11		T7	4
valid_sources[0x3c]	2332	1			T7	2		T8	4		T10	5
valid_sources[0x3d]	2361	1			T6	23		T7	7		T8	3
valid_sources[0x3e]	4032	1			T4	5		T7	8		T8	4
valid_sources[0x3f]	2929	1			T3	43		T6	11		T7	15
valid_sources[0x40]	3948	1			T6	23		T7	12		T8	2
valid_sources[0x41]	3738	1			T7	10		T8	6		T35	4
valid_sources[0x42]	2560	1			T7	9		T8	7		T9	5
valid_sources[0x43]	2640	1			T3	10		T5	2		T7	9
valid_sources[0x44]	2923	1			T6	873		T7	6		T8	2
valid_sources[0x45]	2570	1			T6	25		T7	10		T8	1
valid_sources[0x46]	2376	1			T7	3		T8	5		T9	4
valid_sources[0x47]	4549	1			T7	7		T8	3		T9	1
valid_sources[0x48]	9091	1			T5	2		T6	21		T7	2
valid_sources[0x49]	3266	1			T5	1		T6	12		T7	5
valid_sources[0x4a]	2554	1			T7	5		T8	3		T35	3
valid_sources[0x4b]	5613	1			T6	1837		T7	3		T8	7
valid_sources[0x4c]	2780	1			T5	1		T6	12		T7	10
valid_sources[0x4d]	2870	1			T8	6		T9	1		T35	10
valid_sources[0x4e]	3263	1			T5	1		T7	11		T8	4
valid_sources[0x4f]	3488	1			T6	11		T7	5		T8	2
valid_sources[0x50]	2573	1			T7	13		T8	6		T9	1
valid_sources[0x51]	3289	1			T5	2		T7	11		T8	3
valid_sources[0x52]	2741	1			T5	1		T6	23		T7	1
valid_sources[0x53]	3080	1			T7	4		T8	9		T35	3
valid_sources[0x54]	2650	1			T4	2		T6	92		T7	1
valid_sources[0x55]	3549	1			T6	12		T7	10		T8	4
valid_sources[0x56]	5074	1			T6	2		T7	9		T8	5
valid_sources[0x57]	3671	1			T3	14		T6	12		T7	1
valid_sources[0x58]	5652	1			T6	1987		T7	3		T8	3
valid_sources[0x59]	2432	1			T6	24		T7	9		T8	6
valid_sources[0x5a]	2569	1			T7	9		T8	6		T9	2
valid_sources[0x5b]	2287	1			T4	2		T5	1		T6	35
valid_sources[0x5c]	2700	1			T7	4		T8	6		T9	2
valid_sources[0x5d]	2390	1			T7	7		T8	3		T9	1
valid_sources[0x5e]	2215	1			T5	1		T6	12		T7	1
valid_sources[0x5f]	3402	1			T3	2		T5	1		T6	22
valid_sources[0x60]	2301	1			T6	12		T8	5		T9	2
valid_sources[0x61]	2526	1			T5	2		T7	10		T8	2
valid_sources[0x62]	2864	1			T6	22		T7	11		T8	2
valid_sources[0x63]	2255	1			T7	10		T8	2		T35	7
valid_sources[0x64]	3753	1			T5	1		T7	9		T8	4
valid_sources[0x65]	2231	1			T7	11		T8	3		T35	5
valid_sources[0x66]	2117	1			T7	6		T8	2		T10	3
valid_sources[0x67]	2248	1			T6	12		T7	7		T8	5
valid_sources[0x68]	2194	1			T3	13		T7	5		T8	2
valid_sources[0x69]	3684	1			T5	1		T6	497		T7	7
valid_sources[0x6a]	3017	1			T7	10		T8	4		T9	2
valid_sources[0x6b]	2490	1			T6	22		T8	2		T9	3
valid_sources[0x6c]	2711	1			T7	3		T8	3		T35	4
valid_sources[0x6d]	2406	1			T7	3		T8	4		T9	1
valid_sources[0x6e]	2890	1			T6	11		T7	2		T8	2
valid_sources[0x6f]	5054	1			T7	11		T8	2		T35	4
valid_sources[0x70]	2229	1			T7	13		T8	3		T35	1
valid_sources[0x71]	3848	1			T5	1		T6	11		T7	2
valid_sources[0x72]	2198	1			T5	1		T6	12		T7	2
valid_sources[0x73]	2634	1			T6	12		T7	8		T8	3
valid_sources[0x74]	2352	1			T6	12		T7	13		T9	1
valid_sources[0x75]	2215	1			T7	4		T8	5		T14	2
valid_sources[0x76]	2185	1			T5	1		T7	1		T8	1
valid_sources[0x77]	3230	1			T7	6		T8	3		T35	2
valid_sources[0x78]	2368	1			T6	12		T7	12		T8	4
valid_sources[0x79]	2323	1			T3	22		T6	23		T7	17
valid_sources[0x7a]	2300	1			T5	1		T6	1		T7	5
valid_sources[0x7b]	4086	1			T3	9		T5	1		T6	22
valid_sources[0x7c]	2594	1			T7	2		T8	3		T9	3
valid_sources[0x7d]	2325	1			T6	12		T7	5		T8	6
valid_sources[0x7e]	2136	1			T7	1		T8	4		T9	6
valid_sources[0x7f]	2462	1			T5	1		T6	12		T7	18
valid_sources[0x80]	3054	1			T5	1		T7	3		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103762

1

T1

9

T2

86

T3

20

values[0x0]

all_enables

biggest_size

67091

1

T1

6

T2

77

T3

23

values[0x1]

all_enables

biggest_size

36320

1

T1

1

T2

33

T3

12