SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34864 | 1 | T1 | 1 | T2 | 398 | T8 | 402 | ||||
others[1] | 34719 | 1 | T2 | 383 | T8 | 367 | T23 | 281 | ||||
others[2] | 35335 | 1 | T2 | 404 | T8 | 410 | T23 | 329 | ||||
others[3] | 58570 | 1 | T2 | 677 | T4 | 1 | T8 | 682 | ||||
false | 20377 | 1 | T1 | 1 | T2 | 50 | T4 | 2 | ||||
true | 30781 | 1 | T1 | 4 | T2 | 101 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35352 | 1 | T2 | 416 | T8 | 371 | T23 | 333 | ||||
others[1] | 34903 | 1 | T2 | 400 | T4 | 1 | T8 | 394 | ||||
others[2] | 34831 | 1 | T2 | 400 | T8 | 426 | T23 | 288 | ||||
others[3] | 58333 | 1 | T2 | 631 | T4 | 1 | T8 | 670 | ||||
false | 12784 | 1 | T1 | 4 | T2 | 50 | T4 | 3 | ||||
true | 23235 | 1 | T1 | 6 | T2 | 101 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 678 | 1 | T6 | 4 | T7 | 1 | T10 | 1 | ||||
others[1] | 761 | 1 | T1 | 1 | T4 | 1 | T6 | 5 | ||||
others[2] | 682 | 1 | T6 | 2 | T7 | 3 | T10 | 1 | ||||
others[3] | 1190 | 1 | T6 | 10 | T7 | 3 | T36 | 1 | ||||
false | 14225 | 1 | T1 | 7 | T2 | 1 | T3 | 1 | ||||
true | 4163 | 1 | T1 | 4 | T4 | 3 | T6 | 38 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |