Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23117155	6490	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23117155	239086	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23117155	9436485	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23117155	239088	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23117155	6490	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23117155	239086	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23117155	9436485	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23117155	239088	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	6490	0	0
T2	37967	23	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	4	0	0
T6	277164	67	0	0
T7	41396	3	0	0
T8	57527	25	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	9	0	0
T23	17028	20	0	0
T35	0	22	0	0
T76	0	1	0	0
T77	0	21	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	239086	0	0
T2	37967	976	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	228	0	0
T6	277164	1723	0	0
T7	41396	105	0	0
T8	57527	1489	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	222	0	0
T23	17028	480	0	0
T35	0	1303	0	0
T76	0	10	0	0
T77	0	428	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	9436485	0	0
T2	37967	19033	0	0
T3	18850	8628	0	0
T4	4782	0	0	0
T5	4491	3077	0	0
T6	277164	130456	0	0
T7	41396	14600	0	0
T8	57527	32594	0	0
T9	6073	3662	0	0
T10	4322	0	0	0
T14	0	13538	0	0
T23	17028	8042	0	0
T35	0	21281	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	239088	0	0
T2	37967	976	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	228	0	0
T6	277164	1723	0	0
T7	41396	105	0	0
T8	57527	1489	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	222	0	0
T23	17028	480	0	0
T35	0	1303	0	0
T76	0	10	0	0
T77	0	428	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	6490	0	0
T2	37967	23	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	4	0	0
T6	277164	67	0	0
T7	41396	3	0	0
T8	57527	25	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	9	0	0
T23	17028	20	0	0
T35	0	22	0	0
T76	0	1	0	0
T77	0	21	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	239086	0	0
T2	37967	976	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	228	0	0
T6	277164	1723	0	0
T7	41396	105	0	0
T8	57527	1489	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	222	0	0
T23	17028	480	0	0
T35	0	1303	0	0
T76	0	10	0	0
T77	0	428	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	9436485	0	0
T2	37967	19033	0	0
T3	18850	8628	0	0
T4	4782	0	0	0
T5	4491	3077	0	0
T6	277164	130456	0	0
T7	41396	14600	0	0
T8	57527	32594	0	0
T9	6073	3662	0	0
T10	4322	0	0	0
T14	0	13538	0	0
T23	17028	8042	0	0
T35	0	21281	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	239088	0	0
T2	37967	976	0	0
T3	18850	0	0	0
T4	4782	0	0	0
T5	4491	228	0	0
T6	277164	1723	0	0
T7	41396	105	0	0
T8	57527	1489	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	222	0	0
T23	17028	480	0	0
T35	0	1303	0	0
T76	0	10	0	0
T77	0	428	0	0