Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23703836	14203	0	0
intr_enable_rd_A	23703836	40041	0	0
reset_en_rd_A	23703836	1678	0	0
reset_en_regwen_rd_A	23703836	1342	0	0
wake_info_capture_dis_rd_A	23703836	1411	0	0
wakeup_en_rd_A	23703836	2846	0	0
wakeup_en_regwen_rd_A	23703836	1428	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	14203	0	0
T6	277164	12	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T21	0	6	0	0
T22	0	49	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T47	0	16	0	0
T48	0	13	0	0
T78	1953	0	0	0
T83	0	17	0	0
T84	0	32	0	0
T97	0	6	0	0
T131	0	11	0	0
T132	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	40041	0	0
T6	277164	2479	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T77	0	168	0	0
T78	1953	0	0	0
T81	0	7	0	0
T82	0	148	0	0
T108	0	32	0	0
T133	0	94	0	0
T134	0	92	0	0
T135	0	57	0	0
T136	0	10	0	0
T137	0	141	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	1678	0	0
T6	277164	16	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T44	0	34	0	0
T47	0	9	0	0
T54	0	68	0	0
T69	0	10	0	0
T78	1953	0	0	0
T97	0	13	0	0
T138	0	6	0	0
T139	0	4	0	0
T140	0	18	0	0
T141	0	1	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	1342	0	0
T6	277164	10	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T44	0	27	0	0
T47	0	5	0	0
T54	0	76	0	0
T55	0	34	0	0
T69	0	7	0	0
T78	1953	0	0	0
T97	0	13	0	0
T139	0	7	0	0
T140	0	13	0	0
T142	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	1411	0	0
T6	277164	16	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T44	0	41	0	0
T47	0	5	0	0
T54	0	55	0	0
T55	0	40	0	0
T69	0	2	0	0
T78	1953	0	0	0
T97	0	21	0	0
T138	0	14	0	0
T140	0	9	0	0
T141	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	2846	0	0
T6	277164	8	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T44	0	10	0	0
T54	0	53	0	0
T55	0	30	0	0
T69	0	7	0	0
T78	1953	0	0	0
T97	0	15	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	2	0	0
T143	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23703836	1428	0	0
T6	277164	8	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T11	15665	0	0	0
T14	34448	0	0	0
T23	17028	0	0	0
T35	43906	0	0	0
T44	0	36	0	0
T47	0	4	0	0
T54	0	42	0	0
T69	0	3	0	0
T78	1953	0	0	0
T97	0	8	0	0
T138	0	10	0	0
T139	0	3	0	0
T140	0	7	0	0
T142	0	5	0	0