Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	69351465	154162	0	0
StatusRise_A	69351465	171903	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69351465	154162	0	0
T1	7656	18	0	0
T2	113901	209	0	0
T3	56550	52	0	0
T4	14346	18	0	0
T5	13473	24	0	0
T6	831492	2130	0	0
T7	124188	403	0	0
T8	172581	212	0	0
T9	18219	50	0	0
T10	12966	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69351465	171903	0	0
T1	7656	24	0	0
T2	113901	212	0	0
T3	56550	54	0	0
T4	14346	21	0	0
T5	13473	29	0	0
T6	831492	2397	0	0
T7	124188	456	0	0
T8	172581	215	0	0
T9	18219	52	0	0
T10	12966	57	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23117155	57205	0	0
StatusRise_A	23117155	63627	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	57205	0	0
T1	2552	6	0	0
T2	37967	85	0	0
T3	18850	20	0	0
T4	4782	6	0	0
T5	4491	9	0	0
T6	277164	777	0	0
T7	41396	142	0	0
T8	57527	85	0	0
T9	6073	19	0	0
T10	4322	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	63627	0	0
T1	2552	8	0	0
T2	37967	86	0	0
T3	18850	21	0	0
T4	4782	7	0	0
T5	4491	11	0	0
T6	277164	875	0	0
T7	41396	162	0	0
T8	57527	86	0	0
T9	6073	20	0	0
T10	4322	19	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23117155	57205	0	0
StatusRise_A	23117155	63627	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	57205	0	0
T1	2552	6	0	0
T2	37967	85	0	0
T3	18850	20	0	0
T4	4782	6	0	0
T5	4491	9	0	0
T6	277164	777	0	0
T7	41396	142	0	0
T8	57527	85	0	0
T9	6073	19	0	0
T10	4322	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	63627	0	0
T1	2552	8	0	0
T2	37967	86	0	0
T3	18850	21	0	0
T4	4782	7	0	0
T5	4491	11	0	0
T6	277164	875	0	0
T7	41396	162	0	0
T8	57527	86	0	0
T9	6073	20	0	0
T10	4322	19	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23117155	39752	0	0
StatusRise_A	23117155	44649	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	39752	0	0
T1	2552	6	0	0
T2	37967	39	0	0
T3	18850	12	0	0
T4	4782	6	0	0
T5	4491	6	0	0
T6	277164	576	0	0
T7	41396	119	0	0
T8	57527	42	0	0
T9	6073	12	0	0
T10	4322	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	44649	0	0
T1	2552	8	0	0
T2	37967	40	0	0
T3	18850	12	0	0
T4	4782	7	0	0
T5	4491	7	0	0
T6	277164	647	0	0
T7	41396	132	0	0
T8	57527	43	0	0
T9	6073	12	0	0
T10	4322	19	0	0