Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23117739	5508	0	0
EscTimeoutStoppedByClReset_A	23117155	3093777	0	0
EscTimeoutTriggersReset_A	5757900	330	0	0
RomAllowActiveState_A	23117155	63230	0	0
RomAllowCheckGoodState_A	23117155	63280	0	0
RomBlockActiveState_A	23117155	30580	0	0
RomBlockCheckGoodState_A	23117155	415993	0	0
RomIntgChkDisFalse_A	23117155	22426461	0	0
RomIntgChkDisTrue_A	23117155	140735	0	0
RstreqChkEsctimeout_A	23117155	4531	0	0
RstreqChkFsmterm_A	23117155	180	0	0
RstreqChkGlbesc_A	23117155	4531	0	0
RstreqChkMainpd_A	23117155	889117	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117739	5508	0	0
T11	15666	217	0	0
T12	0	72	0	0
T13	0	43	0	0
T14	34449	0	0	0
T28	0	36	0	0
T33	0	9	0	0
T36	2932	0	0	0
T76	1185	0	0	0
T77	24614	0	0	0
T78	1954	0	0	0
T79	3637	0	0	0
T82	58440	0	0	0
T104	0	7	0	0
T106	5081	0	0	0
T107	4775	0	0	0
T144	0	54	0	0
T145	0	27	0	0
T146	0	36	0	0
T147	0	30	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	3093777	0	0
T1	2552	225	0	0
T2	37967	6941	0	0
T3	18850	3601	0	0
T4	4782	134	0	0
T5	4491	353	0	0
T6	277164	27398	0	0
T7	41396	4134	0	0
T8	57527	10604	0	0
T9	6073	902	0	0
T10	4322	251	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5757900	330	0	0
T11	196	3	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	13074	0	0	0
T28	0	3	0	0
T33	0	3	0	0
T36	1652	0	0	0
T76	501	0	0	0
T77	9015	0	0	0
T78	549	0	0	0
T79	579	0	0	0
T82	5954	0	0	0
T104	0	3	0	0
T106	1031	0	0	0
T107	1120	0	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	2	0	0
T148	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	63230	0	0
T1	2552	8	0	0
T2	37967	86	0	0
T3	18850	21	0	0
T4	4782	7	0	0
T5	4491	11	0	0
T6	277164	875	0	0
T7	41396	162	0	0
T8	57527	86	0	0
T9	6073	20	0	0
T10	4322	12	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	63280	0	0
T1	2552	8	0	0
T2	37967	86	0	0
T3	18850	21	0	0
T4	4782	7	0	0
T5	4491	11	0	0
T6	277164	875	0	0
T7	41396	162	0	0
T8	57527	86	0	0
T9	6073	20	0	0
T10	4322	13	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	30580	0	0
T1	2552	301	0	0
T2	37967	0	0	0
T3	18850	0	0	0
T4	4782	933	0	0
T5	4491	0	0	0
T6	277164	0	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T23	0	7	0	0
T29	0	1300	0	0
T31	0	3	0	0
T80	0	5	0	0
T149	0	23	0	0
T150	0	25	0	0
T151	0	1192	0	0
T152	0	56	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	415993	0	0
T1	2552	330	0	0
T2	37967	2983	0	0
T3	18850	0	0	0
T4	4782	1093	0	0
T5	4491	115	0	0
T6	277164	2202	0	0
T7	41396	253	0	0
T8	57527	4085	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T14	0	253	0	0
T23	0	1287	0	0
T35	0	3461	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	22426461	0	0
T1	2552	2305	0	0
T2	37967	37912	0	0
T3	18850	18784	0	0
T4	4782	3322	0	0
T5	4491	4299	0	0
T6	277164	269651	0	0
T7	41396	39859	0	0
T8	57527	57471	0	0
T9	6073	5975	0	0
T10	4322	3338	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	140735	0	0
T1	2552	129	0	0
T2	37967	0	0	0
T3	18850	0	0	0
T4	4782	1398	0	0
T5	4491	0	0	0
T6	277164	0	0	0
T7	41396	0	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	0	0	0
T23	0	395	0	0
T77	0	319	0	0
T133	0	390	0	0
T149	0	297	0	0
T153	0	1239	0	0
T154	0	577	0	0
T155	0	504	0	0
T156	0	817	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	4531	0	0
T1	2552	3	0	0
T2	37967	0	0	0
T3	18850	0	0	0
T4	4782	2	0	0
T5	4491	0	0	0
T6	277164	43	0	0
T7	41396	23	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	5	0	0
T11	0	1	0	0
T14	0	3	0	0
T36	0	9	0	0
T37	0	6	0	0
T39	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	180	0	0
T18	43225	40	0	0
T19	0	40	0	0
T20	0	20	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	1706	0	0	0
T27	58670	0	0	0
T28	2479	0	0	0
T29	5309	0	0	0
T30	77069	0	0	0
T31	21755	0	0	0
T32	1840	0	0	0
T33	809	0	0	0
T34	5130	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	4531	0	0
T1	2552	3	0	0
T2	37967	0	0	0
T3	18850	0	0	0
T4	4782	2	0	0
T5	4491	0	0	0
T6	277164	43	0	0
T7	41396	23	0	0
T8	57527	0	0	0
T9	6073	0	0	0
T10	4322	5	0	0
T11	0	1	0	0
T14	0	3	0	0
T36	0	9	0	0
T37	0	6	0	0
T39	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23117155	889117	0	0
T1	2552	420	0	0
T2	37967	4042	0	0
T3	18850	0	0	0
T4	4782	300	0	0
T5	4491	357	0	0
T6	277164	4699	0	0
T7	41396	600	0	0
T8	57527	6658	0	0
T9	6073	0	0	0
T10	4322	142	0	0
T23	0	1674	0	0
T35	0	5333	0	0