Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	483358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187166

1

T1

1

T2

6

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	355148	1			T1	1		T2	35		T3	182
values[0x0]	157337	1			T2	11		T3	29		T4	4
values[0x1]	158039	1			T2	11		T3	33		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	382997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

287527

1

T1

1

T2

18

T3

93

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2153	1			T5	19		T6	1		T12	2
valid_sources[0x01]	2181	1			T8	6		T12	2		T13	59
valid_sources[0x02]	2323	1			T8	4		T12	9		T13	56
valid_sources[0x03]	2260	1			T5	4		T8	1		T12	1
valid_sources[0x04]	2254	1			T5	44		T8	6		T12	11
valid_sources[0x05]	2053	1			T2	1		T3	2		T8	2
valid_sources[0x06]	3103	1			T3	10		T6	1		T12	1
valid_sources[0x07]	2535	1			T8	3		T12	1		T13	50
valid_sources[0x08]	3011	1			T8	5		T12	1		T13	50
valid_sources[0x09]	2114	1			T8	5		T12	3		T13	75
valid_sources[0x0a]	2099	1			T5	5		T8	14		T13	57
valid_sources[0x0b]	1941	1			T8	7		T13	40		T36	2
valid_sources[0x0c]	2058	1			T5	13		T6	1		T12	2
valid_sources[0x0d]	2148	1			T3	2		T8	1		T12	6
valid_sources[0x0e]	2265	1			T6	1		T8	1		T12	3
valid_sources[0x0f]	2121	1			T8	5		T12	8		T13	52
valid_sources[0x10]	2052	1			T12	1		T13	62		T36	1
valid_sources[0x11]	2175	1			T6	1		T12	3		T13	73
valid_sources[0x12]	2110	1			T8	9		T12	1		T13	56
valid_sources[0x13]	2464	1			T6	1		T8	3		T12	2
valid_sources[0x14]	4901	1			T8	6		T13	45		T14	23
valid_sources[0x15]	2120	1			T5	11		T8	2		T13	59
valid_sources[0x16]	2006	1			T3	8		T8	4		T13	59
valid_sources[0x17]	2010	1			T3	1		T8	4		T12	10
valid_sources[0x18]	2773	1			T8	3		T12	2		T13	69
valid_sources[0x19]	2075	1			T8	6		T12	3		T13	51
valid_sources[0x1a]	2644	1			T3	8		T5	42		T8	3
valid_sources[0x1b]	2140	1			T8	1		T13	58		T51	1
valid_sources[0x1c]	2388	1			T3	7		T8	2		T12	4
valid_sources[0x1d]	2320	1			T8	11		T13	52		T36	2
valid_sources[0x1e]	2146	1			T5	25		T8	7		T12	4
valid_sources[0x1f]	2306	1			T5	8		T12	1		T13	61
valid_sources[0x20]	3424	1			T3	3		T8	4		T13	49
valid_sources[0x21]	2014	1			T6	2		T8	7		T12	5
valid_sources[0x22]	7996	1			T8	2		T12	7		T13	61
valid_sources[0x23]	3222	1			T5	44		T12	1		T13	52
valid_sources[0x24]	2600	1			T8	4		T13	55		T36	1
valid_sources[0x25]	3162	1			T8	2		T13	50		T36	1
valid_sources[0x26]	2106	1			T5	4		T6	1		T8	1
valid_sources[0x27]	3948	1			T8	6		T12	4		T13	66
valid_sources[0x28]	1937	1			T8	2		T13	57		T36	1
valid_sources[0x29]	3186	1			T6	1		T8	3		T13	51
valid_sources[0x2a]	1950	1			T8	3		T12	4		T13	55
valid_sources[0x2b]	1995	1			T2	2		T8	1		T12	2
valid_sources[0x2c]	1941	1			T5	3		T8	2		T12	5
valid_sources[0x2d]	2193	1			T2	2		T8	10		T12	3
valid_sources[0x2e]	2134	1			T8	5		T12	4		T13	57
valid_sources[0x2f]	3480	1			T8	2		T12	7		T13	55
valid_sources[0x30]	2623	1			T6	1		T8	8		T12	2
valid_sources[0x31]	3924	1			T3	12		T8	8		T12	8
valid_sources[0x32]	3114	1			T8	3		T12	3		T13	57
valid_sources[0x33]	2205	1			T3	2		T8	9		T12	12
valid_sources[0x34]	2068	1			T2	2		T5	7		T8	3
valid_sources[0x35]	3039	1			T3	5		T12	5		T13	55
valid_sources[0x36]	2041	1			T8	2		T13	67		T14	10
valid_sources[0x37]	2297	1			T2	2		T5	17		T8	2
valid_sources[0x38]	2901	1			T12	9		T13	49		T36	1
valid_sources[0x39]	2078	1			T3	5		T8	2		T12	4
valid_sources[0x3a]	2709	1			T12	3		T13	53		T51	1
valid_sources[0x3b]	2329	1			T2	1		T8	4		T12	10
valid_sources[0x3c]	2646	1			T8	4		T12	3		T13	50
valid_sources[0x3d]	3510	1			T3	1		T5	11		T8	5
valid_sources[0x3e]	2581	1			T8	3		T12	1		T13	73
valid_sources[0x3f]	2193	1			T2	2		T8	2		T13	69
valid_sources[0x40]	2072	1			T6	1		T8	4		T12	1
valid_sources[0x41]	3307	1			T6	1		T8	2		T13	61
valid_sources[0x42]	3238	1			T8	4		T12	13		T13	71
valid_sources[0x43]	2112	1			T8	2		T12	5		T13	44
valid_sources[0x44]	1934	1			T5	25		T6	1		T8	3
valid_sources[0x45]	2167	1			T3	5		T8	10		T13	47
valid_sources[0x46]	2102	1			T12	1		T13	49		T14	1
valid_sources[0x47]	4131	1			T8	3		T12	8		T13	50
valid_sources[0x48]	1990	1			T6	2		T8	3		T12	5
valid_sources[0x49]	3820	1			T8	5		T12	2		T13	59
valid_sources[0x4a]	4519	1			T5	22		T8	1		T12	11
valid_sources[0x4b]	2918	1			T8	4		T13	51		T51	2
valid_sources[0x4c]	2339	1			T8	1		T12	4		T13	68
valid_sources[0x4d]	2349	1			T3	2		T5	15		T8	4
valid_sources[0x4e]	2850	1			T3	10		T6	2		T12	13
valid_sources[0x4f]	2143	1			T8	4		T13	68		T36	3
valid_sources[0x50]	2978	1			T3	3		T8	6		T12	1
valid_sources[0x51]	2148	1			T5	22		T8	1		T12	4
valid_sources[0x52]	2699	1			T8	4		T12	6		T13	57
valid_sources[0x53]	2915	1			T6	2		T8	2		T12	2
valid_sources[0x54]	2915	1			T8	1		T12	2		T13	62
valid_sources[0x55]	2828	1			T6	2		T8	1		T12	9
valid_sources[0x56]	4374	1			T12	3		T13	48		T14	33
valid_sources[0x57]	2397	1			T8	2		T12	4		T13	48
valid_sources[0x58]	2199	1			T8	4		T12	2		T13	73
valid_sources[0x59]	1961	1			T8	3		T12	3		T13	53
valid_sources[0x5a]	2099	1			T6	2		T8	2		T12	5
valid_sources[0x5b]	2397	1			T8	1		T12	6		T13	48
valid_sources[0x5c]	3284	1			T2	2		T8	5		T12	2
valid_sources[0x5d]	7266	1			T5	19		T8	2		T12	4
valid_sources[0x5e]	2262	1			T2	1		T12	10		T13	52
valid_sources[0x5f]	2477	1			T8	2		T13	49		T14	5
valid_sources[0x60]	2663	1			T3	7		T8	2		T12	3
valid_sources[0x61]	2194	1			T5	21		T8	7		T13	72
valid_sources[0x62]	4363	1			T3	1		T8	4		T12	2
valid_sources[0x63]	4533	1			T8	1		T13	71		T36	3
valid_sources[0x64]	2265	1			T8	2		T12	1		T13	49
valid_sources[0x65]	2157	1			T8	4		T12	10		T13	63
valid_sources[0x66]	2296	1			T8	6		T12	2		T13	60
valid_sources[0x67]	2319	1			T5	11		T8	6		T12	1
valid_sources[0x68]	2324	1			T2	3		T8	3		T12	8
valid_sources[0x69]	2136	1			T8	1		T13	64		T51	1
valid_sources[0x6a]	3068	1			T8	4		T12	1		T13	56
valid_sources[0x6b]	2139	1			T6	1		T8	1		T12	2
valid_sources[0x6c]	2115	1			T2	3		T3	3		T8	2
valid_sources[0x6d]	2843	1			T6	2		T8	5		T12	5
valid_sources[0x6e]	2154	1			T5	5		T8	4		T13	61
valid_sources[0x6f]	3048	1			T2	4		T3	12		T6	2
valid_sources[0x70]	2920	1			T8	3		T13	63		T14	3
valid_sources[0x71]	2025	1			T2	5		T5	13		T8	7
valid_sources[0x72]	2485	1			T8	2		T12	1		T13	53
valid_sources[0x73]	2227	1			T8	1		T12	1		T13	49
valid_sources[0x74]	1987	1			T6	2		T8	5		T12	3
valid_sources[0x75]	4059	1			T8	8		T13	48		T36	1
valid_sources[0x76]	2226	1			T8	1		T13	55		T36	4
valid_sources[0x77]	7526	1			T8	8		T12	1		T13	65
valid_sources[0x78]	2275	1			T8	2		T12	2		T13	53
valid_sources[0x79]	2091	1			T6	6		T8	2		T12	4
valid_sources[0x7a]	2473	1			T8	3		T12	7		T13	69
valid_sources[0x7b]	2209	1			T2	7		T3	5		T5	25
valid_sources[0x7c]	3369	1			T5	1		T6	1		T8	9
valid_sources[0x7d]	3120	1			T8	1		T12	2		T13	63
valid_sources[0x7e]	1918	1			T8	2		T13	53		T36	2
valid_sources[0x7f]	1875	1			T8	1		T12	12		T13	57
valid_sources[0x80]	1886	1			T6	1		T8	1		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

96601

1

T1

1

T2

5

T3

16

values[0x0]

all_enables

biggest_size

58437

1

T2

1

T3

13

T4

3

values[0x1]

all_enables

biggest_size

32128

1

T3

6

T4

1

T5

49