SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35037 | 1 | T2 | 1 | T5 | 419 | T8 | 399 | ||||
others[1] | 35026 | 1 | T2 | 1 | T5 | 349 | T8 | 367 | ||||
others[2] | 34907 | 1 | T5 | 407 | T8 | 416 | T12 | 407 | ||||
others[3] | 58601 | 1 | T2 | 2 | T5 | 691 | T8 | 680 | ||||
false | 17790 | 1 | T2 | 1 | T5 | 50 | T8 | 50 | ||||
true | 27553 | 1 | T1 | 1 | T2 | 3 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35066 | 1 | T5 | 426 | T8 | 394 | T12 | 392 | ||||
others[1] | 34974 | 1 | T5 | 386 | T8 | 399 | T12 | 411 | ||||
others[2] | 34883 | 1 | T5 | 421 | T8 | 409 | T12 | 387 | ||||
others[3] | 58510 | 1 | T2 | 1 | T5 | 651 | T8 | 659 | ||||
false | 11485 | 1 | T2 | 3 | T5 | 50 | T8 | 50 | ||||
true | 21322 | 1 | T1 | 1 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 646 | 1 | T3 | 6 | T6 | 1 | T13 | 11 | ||||
others[1] | 667 | 1 | T3 | 4 | T13 | 5 | T14 | 1 | ||||
others[2] | 655 | 1 | T3 | 4 | T13 | 12 | T14 | 1 | ||||
others[3] | 1091 | 1 | T2 | 1 | T3 | 9 | T4 | 1 | ||||
false | 13497 | 1 | T1 | 1 | T2 | 6 | T3 | 6 | ||||
true | 4264 | 1 | T2 | 3 | T3 | 5 | T6 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |