Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T12

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23783344	5802	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23783344	253790	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23783344	9672625	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23783344	253779	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23783344	5802	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23783344	253790	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23783344	9672625	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23783344	253779	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	5802	0	0
T5	63046	25	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	27	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	26	0	0
T13	548541	89	0	0
T14	0	9	0	0
T22	0	21	0	0
T36	0	6	0	0
T40	0	1	0	0
T42	0	3	0	0
T51	2063	0	0	0
T78	0	1	0	0
T79	3034	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	253790	0	0
T5	63046	1800	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	979	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	1960	0	0
T13	548541	5472	0	0
T14	0	662	0	0
T22	0	785	0	0
T36	0	520	0	0
T40	0	87	0	0
T42	0	258	0	0
T51	2063	0	0	0
T78	0	13	0	0
T79	3034	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	9672625	0	0
T5	63046	39193	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	20975	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	31472	0	0
T13	548541	224623	0	0
T14	0	43513	0	0
T36	0	6835	0	0
T40	0	57	0	0
T51	2063	217	0	0
T78	0	1622	0	0
T79	3034	0	0	0
T80	0	1137	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	253779	0	0
T5	63046	1800	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	976	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	1960	0	0
T13	548541	5472	0	0
T14	0	662	0	0
T22	0	785	0	0
T36	0	520	0	0
T40	0	87	0	0
T42	0	258	0	0
T51	2063	0	0	0
T78	0	13	0	0
T79	3034	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	5802	0	0
T5	63046	25	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	27	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	26	0	0
T13	548541	89	0	0
T14	0	9	0	0
T22	0	21	0	0
T36	0	6	0	0
T40	0	1	0	0
T42	0	3	0	0
T51	2063	0	0	0
T78	0	1	0	0
T79	3034	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	253790	0	0
T5	63046	1800	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	979	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	1960	0	0
T13	548541	5472	0	0
T14	0	662	0	0
T22	0	785	0	0
T36	0	520	0	0
T40	0	87	0	0
T42	0	258	0	0
T51	2063	0	0	0
T78	0	13	0	0
T79	3034	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	9672625	0	0
T5	63046	39193	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	20975	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	31472	0	0
T13	548541	224623	0	0
T14	0	43513	0	0
T36	0	6835	0	0
T40	0	57	0	0
T51	2063	217	0	0
T78	0	1622	0	0
T79	3034	0	0	0
T80	0	1137	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	253779	0	0
T5	63046	1800	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	976	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	1960	0	0
T13	548541	5472	0	0
T14	0	662	0	0
T22	0	785	0	0
T36	0	520	0	0
T40	0	87	0	0
T42	0	258	0	0
T51	2063	0	0	0
T78	0	13	0	0
T79	3034	0	0	0