Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24359738	15221	0	0
intr_enable_rd_A	24359738	35968	0	0
reset_en_rd_A	24359738	2256	0	0
reset_en_regwen_rd_A	24359738	2043	0	0
wake_info_capture_dis_rd_A	24359738	1948	0	0
wakeup_en_rd_A	24359738	2822	0	0
wakeup_en_regwen_rd_A	24359738	2108	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	15221	0	0
T11	15136	0	0	0
T13	548541	115	0	0
T14	94824	0	0	0
T15	0	26	0	0
T21	0	45	0	0
T36	19704	0	0	0
T37	2953	0	0	0
T40	1611	0	0	0
T45	0	8	0	0
T51	2063	0	0	0
T73	0	80	0	0
T74	0	8	0	0
T78	2550	0	0	0
T80	3223	0	0	0
T81	2773	0	0	0
T121	0	28	0	0
T122	0	11	0	0
T123	0	1	0	0
T124	0	87	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	35968	0	0
T2	3153	18	0	0
T3	4334	116	0	0
T4	1847	7	0	0
T5	63046	0	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	0	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	0	0	0
T22	0	176	0	0
T51	0	11	0	0
T81	0	12	0	0
T91	0	117	0	0
T125	0	70	0	0
T126	0	13	0	0
T127	0	20	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	2256	0	0
T53	0	76	0	0
T60	0	51	0	0
T64	0	53	0	0
T88	0	9	0	0
T110	0	467	0	0
T128	98815	2	0	0
T129	0	9	0	0
T130	0	2	0	0
T131	0	16	0	0
T132	0	15	0	0
T133	1585	0	0	0
T134	3049	0	0	0
T135	3262	0	0	0
T136	7970	0	0	0
T137	2170	0	0	0
T138	15444	0	0	0
T139	2228	0	0	0
T140	2425	0	0	0
T141	3467	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	2043	0	0
T60	0	50	0	0
T64	0	20	0	0
T88	0	3	0	0
T128	98815	1	0	0
T129	0	4	0	0
T130	0	2	0	0
T131	0	5	0	0
T132	0	20	0	0
T133	1585	0	0	0
T134	3049	0	0	0
T135	3262	0	0	0
T136	7970	0	0	0
T137	2170	0	0	0
T138	15444	0	0	0
T139	2228	0	0	0
T140	2425	0	0	0
T141	3467	0	0	0
T142	0	7	0	0
T143	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	1948	0	0
T60	0	43	0	0
T64	0	25	0	0
T86	230830	6	0	0
T87	91119	0	0	0
T88	0	6	0	0
T128	0	2	0	0
T129	0	8	0	0
T130	0	8	0	0
T131	0	17	0	0
T142	0	11	0	0
T144	0	6	0	0
T145	1044	0	0	0
T146	940	0	0	0
T147	19212	0	0	0
T148	1218	0	0	0
T149	1673	0	0	0
T150	9325	0	0	0
T151	8345	0	0	0
T152	1662	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	2822	0	0
T60	0	53	0	0
T64	0	23	0	0
T88	0	3	0	0
T128	98815	6	0	0
T129	0	1	0	0
T130	0	4	0	0
T131	0	12	0	0
T132	0	18	0	0
T133	1585	0	0	0
T134	3049	0	0	0
T135	3262	0	0	0
T136	7970	0	0	0
T137	2170	0	0	0
T138	15444	0	0	0
T139	2228	0	0	0
T140	2425	0	0	0
T141	3467	0	0	0
T143	0	2	0	0
T144	0	4	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24359738	2108	0	0
T60	0	57	0	0
T64	0	29	0	0
T88	0	2	0	0
T128	98815	6	0	0
T129	0	1	0	0
T131	0	6	0	0
T132	0	25	0	0
T133	1585	0	0	0
T134	3049	0	0	0
T135	3262	0	0	0
T136	7970	0	0	0
T137	2170	0	0	0
T138	15444	0	0	0
T139	2228	0	0	0
T140	2425	0	0	0
T141	3467	0	0	0
T142	0	10	0	0
T143	0	8	0	0
T144	0	6	0	0