Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71350032	136851	0	0
StatusRise_A	71350032	153051	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71350032	136851	0	0
T1	46821	3	0	0
T2	9459	18	0	0
T3	13002	15	0	0
T4	5541	3	0	0
T5	189138	213	0	0
T6	9327	54	0	0
T7	7839	0	0	0
T8	103884	211	0	0
T9	8745	0	0	0
T10	2472	3	0	0
T12	0	210	0	0
T13	0	2719	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71350032	153051	0	0
T1	46821	6	0	0
T2	9459	24	0	0
T3	13002	18	0	0
T4	5541	6	0	0
T5	189138	219	0	0
T6	9327	60	0	0
T7	7839	9	0	0
T8	103884	216	0	0
T9	8745	12	0	0
T10	2472	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23783344	50706	0	0
StatusRise_A	23783344	56529	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	50706	0	0
T1	15607	1	0	0
T2	3153	6	0	0
T3	4334	5	0	0
T4	1847	1	0	0
T5	63046	83	0	0
T6	3109	18	0	0
T7	2613	0	0	0
T8	34628	84	0	0
T9	2915	0	0	0
T10	824	1	0	0
T12	0	86	0	0
T13	0	981	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	56529	0	0
T1	15607	2	0	0
T2	3153	8	0	0
T3	4334	6	0	0
T4	1847	2	0	0
T5	63046	85	0	0
T6	3109	20	0	0
T7	2613	3	0	0
T8	34628	86	0	0
T9	2915	4	0	0
T10	824	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23783344	50706	0	0
StatusRise_A	23783344	56529	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	50706	0	0
T1	15607	1	0	0
T2	3153	6	0	0
T3	4334	5	0	0
T4	1847	1	0	0
T5	63046	83	0	0
T6	3109	18	0	0
T7	2613	0	0	0
T8	34628	84	0	0
T9	2915	0	0	0
T10	824	1	0	0
T12	0	86	0	0
T13	0	981	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	56529	0	0
T1	15607	2	0	0
T2	3153	8	0	0
T3	4334	6	0	0
T4	1847	2	0	0
T5	63046	85	0	0
T6	3109	20	0	0
T7	2613	3	0	0
T8	34628	86	0	0
T9	2915	4	0	0
T10	824	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23783344	35439	0	0
StatusRise_A	23783344	39993	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	35439	0	0
T1	15607	1	0	0
T2	3153	6	0	0
T3	4334	5	0	0
T4	1847	1	0	0
T5	63046	47	0	0
T6	3109	18	0	0
T7	2613	0	0	0
T8	34628	43	0	0
T9	2915	0	0	0
T10	824	1	0	0
T12	0	38	0	0
T13	0	757	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	39993	0	0
T1	15607	2	0	0
T2	3153	8	0	0
T3	4334	6	0	0
T4	1847	2	0	0
T5	63046	49	0	0
T6	3109	20	0	0
T7	2613	3	0	0
T8	34628	44	0	0
T9	2915	4	0	0
T10	824	3	0	0