Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23783949	6319	0	0
EscTimeoutStoppedByClReset_A	23783344	3403584	0	0
EscTimeoutTriggersReset_A	4649527	339	0	0
RomAllowActiveState_A	23783344	56147	0	0
RomAllowCheckGoodState_A	23783344	56198	0	0
RomBlockActiveState_A	23783344	26709	0	0
RomBlockCheckGoodState_A	23783344	417411	0	0
RomIntgChkDisFalse_A	23783344	23141795	0	0
RomIntgChkDisTrue_A	23783344	137774	0	0
RstreqChkEsctimeout_A	23783344	4415	0	0
RstreqChkFsmterm_A	23783344	180	0	0
RstreqChkGlbesc_A	23783344	4415	0	0
RstreqChkMainpd_A	23783344	992200	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783949	6319	0	0
T1	15608	130	0	0
T2	3153	0	0	0
T3	4335	0	0	0
T4	1848	0	0	0
T5	63047	0	0	0
T6	3110	0	0	0
T7	2614	0	0	0
T8	34629	0	0	0
T9	2915	0	0	0
T10	825	0	0	0
T11	0	7	0	0
T153	0	113	0	0
T154	0	59	0	0
T155	0	9	0	0
T156	0	10	0	0
T157	0	16	0	0
T158	0	52	0	0
T159	0	117	0	0
T160	0	55	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	3403584	0	0
T1	15607	9	0	0
T2	3153	241	0	0
T3	4334	61	0	0
T4	1847	14	0	0
T5	63046	9702	0	0
T6	3109	348	0	0
T7	2613	14	0	0
T8	34628	4494	0	0
T9	2915	8	0	0
T10	824	27	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4649527	339	0	0
T1	197	2	0	0
T2	519	0	0	0
T3	1231	0	0	0
T4	152	0	0	0
T5	6282	0	0	0
T6	1129	0	0	0
T7	238	0	0	0
T8	6347	0	0	0
T9	273	0	0	0
T10	280	5	0	0
T11	0	3	0	0
T153	0	2	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	5	0	0
T157	0	2	0	0
T161	0	6	0	0
T162	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	56147	0	0
T1	15607	2	0	0
T2	3153	8	0	0
T3	4334	6	0	0
T4	1847	2	0	0
T5	63046	85	0	0
T6	3109	13	0	0
T7	2613	3	0	0
T8	34628	86	0	0
T9	2915	4	0	0
T10	824	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	56198	0	0
T1	15607	2	0	0
T2	3153	8	0	0
T3	4334	6	0	0
T4	1847	2	0	0
T5	63046	85	0	0
T6	3109	14	0	0
T7	2613	3	0	0
T8	34628	86	0	0
T9	2915	4	0	0
T10	824	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	26709	0	0
T2	3153	470	0	0
T3	4334	0	0	0
T4	1847	0	0	0
T5	63046	0	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	0	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	0	0	0
T24	0	286	0	0
T44	0	266	0	0
T163	0	550	0	0
T164	0	499	0	0
T165	0	5	0	0
T166	0	283	0	0
T167	0	219	0	0
T168	0	11	0	0
T169	0	216	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	417411	0	0
T2	3153	281	0	0
T3	4334	0	0	0
T4	1847	0	0	0
T5	63046	4105	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	2286	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	4067	0	0
T13	0	3617	0	0
T14	0	483	0	0
T15	0	1788	0	0
T22	0	2225	0	0
T36	0	437	0	0
T170	0	68	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	23141795	0	0
T1	15607	15527	0	0
T2	3153	1967	0	0
T3	4334	4242	0	0
T4	1847	1768	0	0
T5	63046	62866	0	0
T6	3109	2211	0	0
T7	2613	2404	0	0
T8	34628	34484	0	0
T9	2915	2568	0	0
T10	824	668	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	137774	0	0
T2	3153	1078	0	0
T3	4334	0	0	0
T4	1847	0	0	0
T5	63046	0	0	0
T6	3109	0	0	0
T7	2613	0	0	0
T8	34628	0	0	0
T9	2915	0	0	0
T10	824	0	0	0
T12	55228	0	0	0
T22	0	1209	0	0
T23	0	1038	0	0
T24	0	804	0	0
T44	0	671	0	0
T163	0	106	0	0
T164	0	136	0	0
T171	0	1131	0	0
T172	0	2777	0	0
T173	0	597	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	4415	0	0
T1	15607	1	0	0
T2	3153	1	0	0
T3	4334	0	0	0
T4	1847	1	0	0
T5	63046	0	0	0
T6	3109	6	0	0
T7	2613	0	0	0
T8	34628	0	0	0
T9	2915	0	0	0
T10	824	1	0	0
T11	0	1	0	0
T13	0	128	0	0
T14	0	8	0	0
T15	0	45	0	0
T37	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	180	0	0
T18	39465	40	0	0
T19	0	40	0	0
T20	0	40	0	0
T25	0	20	0	0
T26	0	40	0	0
T27	1828	0	0	0
T28	10022	0	0	0
T29	5007	0	0	0
T30	2848	0	0	0
T31	4817	0	0	0
T32	50873	0	0	0
T33	1640	0	0	0
T34	15812	0	0	0
T35	3594	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	4415	0	0
T1	15607	1	0	0
T2	3153	1	0	0
T3	4334	0	0	0
T4	1847	1	0	0
T5	63046	0	0	0
T6	3109	6	0	0
T7	2613	0	0	0
T8	34628	0	0	0
T9	2915	0	0	0
T10	824	1	0	0
T11	0	1	0	0
T13	0	128	0	0
T14	0	8	0	0
T15	0	45	0	0
T37	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23783344	992200	0	0
T2	3153	387	0	0
T3	4334	0	0	0
T4	1847	0	0	0
T5	63046	8587	0	0
T6	3109	164	0	0
T7	2613	6	0	0
T8	34628	3644	0	0
T9	2915	16	0	0
T10	824	0	0	0
T12	55228	8260	0	0
T13	0	29281	0	0
T36	0	1630	0	0
T79	0	11	0	0