Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187703

1

T1

4

T2

27

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	358095	1			T1	14		T2	182		T3	72
values[0x0]	161723	1			T1	3		T2	30		T3	42
values[0x1]	163443	1			T1	7		T2	32		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	392380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

290881

1

T1

11

T2

90

T3

71

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2102	1			T2	1		T18	2		T24	51
valid_sources[0x01]	2834	1			T2	2		T7	1		T8	1
valid_sources[0x02]	2311	1			T3	29		T10	1		T18	11
valid_sources[0x03]	2074	1			T10	5		T18	18		T19	10
valid_sources[0x04]	2092	1			T29	3		T18	8		T19	2
valid_sources[0x05]	1973	1			T2	2		T10	6		T18	20
valid_sources[0x06]	2392	1			T2	1		T8	1		T17	2
valid_sources[0x07]	2254	1			T18	4		T19	1		T42	2
valid_sources[0x08]	2039	1			T18	13		T19	5		T63	1
valid_sources[0x09]	2100	1			T2	2		T10	5		T18	13
valid_sources[0x0a]	2234	1			T2	1		T18	3		T19	8
valid_sources[0x0b]	2246	1			T41	2		T18	10		T19	2
valid_sources[0x0c]	2103	1			T2	1		T8	1		T18	7
valid_sources[0x0d]	2173	1			T7	1		T18	6		T19	1
valid_sources[0x0e]	2303	1			T2	6		T10	1		T17	1
valid_sources[0x0f]	2394	1			T2	2		T10	6		T29	30
valid_sources[0x10]	2175	1			T10	5		T17	1		T18	15
valid_sources[0x11]	2026	1			T18	9		T19	2		T20	12
valid_sources[0x12]	2300	1			T8	2		T29	7		T18	7
valid_sources[0x13]	2044	1			T7	2		T18	6		T19	1
valid_sources[0x14]	2115	1			T2	1		T18	3		T78	5
valid_sources[0x15]	6446	1			T18	9		T19	3		T63	1
valid_sources[0x16]	2814	1			T7	4		T41	1		T18	7
valid_sources[0x17]	2431	1			T2	1		T7	1		T13	13
valid_sources[0x18]	2115	1			T2	1		T8	1		T13	17
valid_sources[0x19]	3193	1			T41	1		T18	12		T19	9
valid_sources[0x1a]	2082	1			T2	2		T8	1		T10	1
valid_sources[0x1b]	4012	1			T2	1		T8	1		T10	1
valid_sources[0x1c]	2281	1			T2	2		T10	2		T13	6
valid_sources[0x1d]	2051	1			T2	1		T18	8		T19	6
valid_sources[0x1e]	2810	1			T2	1		T7	3		T17	2
valid_sources[0x1f]	2426	1			T2	3		T41	1		T18	5
valid_sources[0x20]	2042	1			T1	2		T2	2		T41	1
valid_sources[0x21]	2963	1			T17	1		T18	7		T19	7
valid_sources[0x22]	2005	1			T2	2		T18	10		T19	8
valid_sources[0x23]	2107	1			T2	4		T18	5		T19	3
valid_sources[0x24]	2308	1			T41	1		T18	18		T19	7
valid_sources[0x25]	2160	1			T10	4		T18	9		T19	9
valid_sources[0x26]	2799	1			T18	6		T19	1		T57	1
valid_sources[0x27]	2280	1			T18	4		T19	15		T63	1
valid_sources[0x28]	2412	1			T41	3		T18	6		T63	1
valid_sources[0x29]	3377	1			T3	5		T10	2		T18	19
valid_sources[0x2a]	2156	1			T18	5		T19	11		T26	3
valid_sources[0x2b]	2359	1			T2	2		T3	35		T17	5
valid_sources[0x2c]	2641	1			T2	3		T7	1		T18	6
valid_sources[0x2d]	2646	1			T29	24		T18	8		T19	9
valid_sources[0x2e]	2358	1			T18	9		T19	13		T63	1
valid_sources[0x2f]	2196	1			T2	1		T10	3		T41	1
valid_sources[0x30]	4469	1			T10	12		T18	21		T19	3
valid_sources[0x31]	2079	1			T8	1		T18	5		T63	2
valid_sources[0x32]	3017	1			T2	4		T18	8		T19	3
valid_sources[0x33]	2231	1			T2	1		T7	1		T8	1
valid_sources[0x34]	2014	1			T10	1		T41	1		T18	6
valid_sources[0x35]	2586	1			T2	1		T7	1		T29	28
valid_sources[0x36]	2121	1			T18	11		T19	4		T20	11
valid_sources[0x37]	2897	1			T2	3		T10	4		T17	3
valid_sources[0x38]	2451	1			T18	10		T19	17		T63	2
valid_sources[0x39]	2230	1			T2	3		T18	9		T63	3
valid_sources[0x3a]	2938	1			T2	5		T18	12		T19	2
valid_sources[0x3b]	2472	1			T2	1		T18	8		T19	5
valid_sources[0x3c]	2365	1			T2	3		T18	16		T19	2
valid_sources[0x3d]	2036	1			T2	2		T8	1		T18	19
valid_sources[0x3e]	2164	1			T1	1		T2	1		T17	2
valid_sources[0x3f]	2308	1			T41	1		T18	14		T63	1
valid_sources[0x40]	2452	1			T2	1		T8	1		T18	10
valid_sources[0x41]	3138	1			T2	2		T18	12		T19	6
valid_sources[0x42]	3646	1			T18	16		T19	5		T20	12
valid_sources[0x43]	4246	1			T8	1		T41	1		T18	6
valid_sources[0x44]	2846	1			T2	6		T18	13		T19	8
valid_sources[0x45]	2910	1			T8	1		T10	5		T18	9
valid_sources[0x46]	2078	1			T13	6		T18	7		T19	1
valid_sources[0x47]	2078	1			T10	1		T18	8		T19	5
valid_sources[0x48]	2771	1			T18	9		T19	2		T63	1
valid_sources[0x49]	2112	1			T7	1		T41	1		T18	8
valid_sources[0x4a]	2963	1			T2	1		T8	1		T10	2
valid_sources[0x4b]	2897	1			T2	3		T7	1		T18	10
valid_sources[0x4c]	2044	1			T2	2		T7	1		T8	1
valid_sources[0x4d]	1986	1			T10	3		T13	12		T18	17
valid_sources[0x4e]	2382	1			T2	1		T3	13		T10	1
valid_sources[0x4f]	3751	1			T10	1		T18	13		T19	2
valid_sources[0x50]	2358	1			T2	1		T13	72		T18	8
valid_sources[0x51]	2218	1			T2	3		T7	1		T17	3
valid_sources[0x52]	2133	1			T10	1		T18	6		T19	4
valid_sources[0x53]	2141	1			T2	3		T7	3		T29	8
valid_sources[0x54]	3510	1			T10	1		T29	2		T18	4
valid_sources[0x55]	2734	1			T1	4		T10	3		T18	15
valid_sources[0x56]	2268	1			T2	4		T18	6		T19	8
valid_sources[0x57]	1948	1			T10	5		T18	12		T19	5
valid_sources[0x58]	2179	1			T8	1		T18	8		T19	6
valid_sources[0x59]	2146	1			T2	2		T10	1		T18	8
valid_sources[0x5a]	2341	1			T8	1		T18	4		T19	3
valid_sources[0x5b]	2197	1			T1	8		T2	3		T3	8
valid_sources[0x5c]	2454	1			T2	1		T18	8		T19	13
valid_sources[0x5d]	3566	1			T18	17		T19	6		T26	2
valid_sources[0x5e]	2085	1			T2	1		T10	2		T18	15
valid_sources[0x5f]	3854	1			T11	244		T18	11		T19	14
valid_sources[0x60]	2978	1			T18	12		T19	3		T24	61
valid_sources[0x61]	1970	1			T2	1		T18	5		T78	3
valid_sources[0x62]	2131	1			T18	9		T19	3		T63	1
valid_sources[0x63]	3709	1			T2	1		T41	1		T18	7
valid_sources[0x64]	2182	1			T7	3		T18	6		T19	4
valid_sources[0x65]	2622	1			T10	1		T41	1		T18	11
valid_sources[0x66]	3390	1			T2	1		T3	20		T10	1
valid_sources[0x67]	2327	1			T2	5		T41	1		T29	31
valid_sources[0x68]	2184	1			T2	2		T8	1		T10	1
valid_sources[0x69]	2332	1			T2	1		T10	2		T41	1
valid_sources[0x6a]	2021	1			T2	1		T10	9		T18	8
valid_sources[0x6b]	2160	1			T2	1		T7	1		T10	4
valid_sources[0x6c]	2133	1			T29	22		T18	9		T19	1
valid_sources[0x6d]	2597	1			T2	1		T18	7		T19	4
valid_sources[0x6e]	4215	1			T29	77		T18	15		T78	5
valid_sources[0x6f]	5331	1			T1	1		T18	17		T19	1
valid_sources[0x70]	3351	1			T10	3		T18	9		T19	8
valid_sources[0x71]	3747	1			T8	1		T18	5		T19	15
valid_sources[0x72]	2838	1			T29	32		T18	12		T19	2
valid_sources[0x73]	3057	1			T8	1		T10	4		T18	11
valid_sources[0x74]	3267	1			T18	14		T78	1		T19	2
valid_sources[0x75]	2219	1			T10	2		T17	1		T41	1
valid_sources[0x76]	2112	1			T8	1		T29	20		T18	11
valid_sources[0x77]	2043	1			T2	2		T41	1		T18	8
valid_sources[0x78]	2250	1			T3	4		T8	2		T18	12
valid_sources[0x79]	2192	1			T10	3		T18	11		T19	6
valid_sources[0x7a]	2057	1			T41	1		T29	14		T18	8
valid_sources[0x7b]	3152	1			T10	7		T18	12		T19	4
valid_sources[0x7c]	2100	1			T2	1		T29	38		T18	5
valid_sources[0x7d]	2478	1			T2	1		T17	2		T41	1
valid_sources[0x7e]	2056	1			T10	4		T41	1		T18	15
valid_sources[0x7f]	2204	1			T10	1		T41	1		T18	10
valid_sources[0x80]	2968	1			T10	1		T18	4		T19	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

95046

1

T1

3

T2

12

T3

23

values[0x0]

all_enables

biggest_size

60030

1

T2

8

T3

18

T7

1

values[0x1]

all_enables

biggest_size

32627

1

T1

1

T2

7

T3

10