SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35334 | 1 | T29 | 367 | T27 | 308 | T25 | 1 | ||||
others[1] | 34984 | 1 | T29 | 393 | T26 | 1 | T27 | 286 | ||||
others[2] | 34947 | 1 | T29 | 430 | T27 | 290 | T165 | 289 | ||||
others[3] | 58105 | 1 | T29 | 655 | T27 | 521 | T165 | 488 | ||||
false | 18124 | 1 | T9 | 32 | T17 | 2 | T29 | 50 | ||||
true | 27807 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35191 | 1 | T29 | 379 | T27 | 262 | T28 | 1 | ||||
others[1] | 35124 | 1 | T29 | 411 | T27 | 298 | T25 | 1 | ||||
others[2] | 35033 | 1 | T29 | 415 | T27 | 310 | T165 | 314 | ||||
others[3] | 58121 | 1 | T17 | 2 | T29 | 657 | T26 | 1 | ||||
false | 11657 | 1 | T9 | 16 | T17 | 2 | T29 | 50 | ||||
true | 21413 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 680 | 1 | T2 | 7 | T10 | 6 | T11 | 5 | ||||
others[1] | 676 | 1 | T2 | 2 | T10 | 5 | T11 | 7 | ||||
others[2] | 688 | 1 | T2 | 4 | T10 | 4 | T11 | 6 | ||||
others[3] | 1106 | 1 | T2 | 9 | T8 | 1 | T10 | 7 | ||||
false | 13281 | 1 | T1 | 1 | T2 | 6 | T3 | 1 | ||||
true | 4066 | 1 | T2 | 4 | T8 | 8 | T10 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |