Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T18,T43

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22192033	5817	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22192033	232249	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22192033	8998269	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22192033	232270	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22192033	5817	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22192033	232249	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22192033	8998269	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22192033	232270	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	5817	0	0
T1	1516	1	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	1	0	0
T8	3082	0	0	0
T9	16579	6	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	14	0	0
T19	0	4	0	0
T20	0	59	0	0
T24	0	31	0	0
T29	0	26	0	0
T43	0	9	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	232249	0	0
T1	1516	12	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	13	0	0
T8	3082	0	0	0
T9	16579	557	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	321	0	0
T19	0	40	0	0
T20	0	1354	0	0
T24	0	2319	0	0
T29	0	1664	0	0
T43	0	821	0	0
T78	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	8998269	0	0
T1	1516	1214	0	0
T2	6130	0	0	0
T3	5729	2112	0	0
T7	2431	1593	0	0
T8	3082	0	0	0
T9	16579	6466	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	2753	0	0
T18	0	22505	0	0
T19	0	16283	0	0
T29	0	33603	0	0
T43	0	9493	0	0
T78	0	768	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	232270	0	0
T1	1516	12	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	13	0	0
T8	3082	0	0	0
T9	16579	557	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	321	0	0
T19	0	40	0	0
T20	0	1354	0	0
T24	0	2323	0	0
T29	0	1664	0	0
T43	0	821	0	0
T78	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	5817	0	0
T1	1516	1	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	1	0	0
T8	3082	0	0	0
T9	16579	6	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	14	0	0
T19	0	4	0	0
T20	0	59	0	0
T24	0	31	0	0
T29	0	26	0	0
T43	0	9	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	232249	0	0
T1	1516	12	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	13	0	0
T8	3082	0	0	0
T9	16579	557	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	321	0	0
T19	0	40	0	0
T20	0	1354	0	0
T24	0	2319	0	0
T29	0	1664	0	0
T43	0	821	0	0
T78	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	8998269	0	0
T1	1516	1214	0	0
T2	6130	0	0	0
T3	5729	2112	0	0
T7	2431	1593	0	0
T8	3082	0	0	0
T9	16579	6466	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	2753	0	0
T18	0	22505	0	0
T19	0	16283	0	0
T29	0	33603	0	0
T43	0	9493	0	0
T78	0	768	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	232270	0	0
T1	1516	12	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	13	0	0
T8	3082	0	0	0
T9	16579	557	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T18	0	321	0	0
T19	0	40	0	0
T20	0	1354	0	0
T24	0	2323	0	0
T29	0	1664	0	0
T43	0	821	0	0
T78	0	12	0	0