Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22823853	16708	0	0
intr_enable_rd_A	22823853	37237	0	0
reset_en_rd_A	22823853	1279	0	0
reset_en_regwen_rd_A	22823853	1209	0	0
wake_info_capture_dis_rd_A	22823853	1122	0	0
wakeup_en_rd_A	22823853	1906	0	0
wakeup_en_regwen_rd_A	22823853	1121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	16708	0	0
T15	15085	0	0	0
T16	1345	0	0	0
T20	254384	5	0	0
T21	3046	0	0	0
T24	309060	54	0	0
T25	0	119	0	0
T26	4146	0	0	0
T44	7305	0	0	0
T45	1480	0	0	0
T52	0	139	0	0
T57	13679	0	0	0
T90	1397	0	0	0
T131	0	17	0	0
T132	0	12	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	5	0	0
T136	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	37237	0	0
T1	1516	1	0	0
T2	6130	0	0	0
T3	5729	0	0	0
T7	2431	0	0	0
T8	3082	0	0	0
T9	16579	0	0	0
T10	4795	85	0	0
T11	4364	134	0	0
T12	9274	61	0	0
T13	6586	58	0	0
T20	0	1502	0	0
T28	0	10	0	0
T79	0	60	0	0
T137	0	8	0	0
T138	0	10	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	1279	0	0
T82	269693	0	0	0
T83	0	4	0	0
T84	0	7	0	0
T91	0	8	0	0
T139	185276	7	0	0
T140	0	6	0	0
T141	0	4	0	0
T142	0	2	0	0
T143	0	5	0	0
T144	0	9	0	0
T145	0	2	0	0
T146	7740	0	0	0
T147	1338	0	0	0
T148	3284	0	0	0
T149	7056	0	0	0
T150	55304	0	0	0
T151	4021	0	0	0
T152	3079	0	0	0
T153	1082	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	1209	0	0
T82	269693	0	0	0
T83	0	8	0	0
T84	0	7	0	0
T91	0	10	0	0
T139	185276	3	0	0
T140	0	6	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	9	0	0
T144	0	5	0	0
T145	0	1	0	0
T146	7740	0	0	0
T147	1338	0	0	0
T148	3284	0	0	0
T149	7056	0	0	0
T150	55304	0	0	0
T151	4021	0	0	0
T152	3079	0	0	0
T153	1082	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	1122	0	0
T55	0	33	0	0
T82	269693	0	0	0
T83	0	8	0	0
T91	0	3	0	0
T109	0	4	0	0
T139	185276	10	0	0
T140	0	7	0	0
T141	0	6	0	0
T143	0	8	0	0
T144	0	9	0	0
T146	7740	0	0	0
T147	1338	0	0	0
T148	3284	0	0	0
T149	7056	0	0	0
T150	55304	0	0	0
T151	4021	0	0	0
T152	3079	0	0	0
T153	1082	0	0	0
T154	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	1906	0	0
T82	269693	0	0	0
T83	0	15	0	0
T84	0	2	0	0
T91	0	14	0	0
T139	185276	7	0	0
T140	0	17	0	0
T141	0	9	0	0
T142	0	3	0	0
T143	0	3	0	0
T144	0	6	0	0
T145	0	3	0	0
T146	7740	0	0	0
T147	1338	0	0	0
T148	3284	0	0	0
T149	7056	0	0	0
T150	55304	0	0	0
T151	4021	0	0	0
T152	3079	0	0	0
T153	1082	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22823853	1121	0	0
T82	269693	0	0	0
T84	0	9	0	0
T91	0	11	0	0
T139	185276	8	0	0
T140	0	13	0	0
T141	0	6	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	7740	0	0	0
T147	1338	0	0	0
T148	3284	0	0	0
T149	7056	0	0	0
T150	55304	0	0	0
T151	4021	0	0	0
T152	3079	0	0	0
T153	1082	0	0	0
T154	0	7	0	0
T155	0	5	0	0