Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66576099	139654	0	0
StatusRise_A	66576099	155669	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66576099	139654	0	0
T1	4548	6	0	0
T2	18390	12	0	0
T3	17187	28	0	0
T7	7293	6	0	0
T8	9246	54	0	0
T9	49737	65	0	0
T10	14385	9	0	0
T11	13092	3	0	0
T12	27822	81	0	0
T13	19758	42	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66576099	155669	0	0
T1	4548	9	0	0
T2	18390	15	0	0
T3	17187	31	0	0
T7	7293	9	0	0
T8	9246	57	0	0
T9	49737	70	0	0
T10	14385	12	0	0
T11	13092	6	0	0
T12	27822	87	0	0
T13	19758	44	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22192033	51803	0	0
StatusRise_A	22192033	57578	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	51803	0	0
T1	1516	2	0	0
T2	6130	4	0	0
T3	5729	11	0	0
T7	2431	2	0	0
T8	3082	18	0	0
T9	16579	28	0	0
T10	4795	3	0	0
T11	4364	1	0	0
T12	9274	27	0	0
T13	6586	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	57578	0	0
T1	1516	3	0	0
T2	6130	5	0	0
T3	5729	12	0	0
T7	2431	3	0	0
T8	3082	19	0	0
T9	16579	30	0	0
T10	4795	4	0	0
T11	4364	2	0	0
T12	9274	29	0	0
T13	6586	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22192033	51803	0	0
StatusRise_A	22192033	57579	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	51803	0	0
T1	1516	2	0	0
T2	6130	4	0	0
T3	5729	11	0	0
T7	2431	2	0	0
T8	3082	18	0	0
T9	16579	28	0	0
T10	4795	3	0	0
T11	4364	1	0	0
T12	9274	27	0	0
T13	6586	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	57579	0	0
T1	1516	3	0	0
T2	6130	5	0	0
T3	5729	12	0	0
T7	2431	3	0	0
T8	3082	19	0	0
T9	16579	30	0	0
T10	4795	4	0	0
T11	4364	2	0	0
T12	9274	29	0	0
T13	6586	17	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22192033	36048	0	0
StatusRise_A	22192033	40512	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	36048	0	0
T1	1516	2	0	0
T2	6130	4	0	0
T3	5729	6	0	0
T7	2431	2	0	0
T8	3082	18	0	0
T9	16579	9	0	0
T10	4795	3	0	0
T11	4364	1	0	0
T12	9274	27	0	0
T13	6586	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	40512	0	0
T1	1516	3	0	0
T2	6130	5	0	0
T3	5729	7	0	0
T7	2431	3	0	0
T8	3082	19	0	0
T9	16579	10	0	0
T10	4795	4	0	0
T11	4364	2	0	0
T12	9274	29	0	0
T13	6586	10	0	0