Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	22192620	5514	0	0
EscTimeoutStoppedByClReset_A	22192033	3085750	0	0
EscTimeoutTriggersReset_A	5107847	323	0	0
RomAllowActiveState_A	22192033	57209	0	0
RomAllowCheckGoodState_A	22192033	57259	0	0
RomBlockActiveState_A	22192033	27874	0	0
RomBlockCheckGoodState_A	22192033	426219	0	0
RomIntgChkDisFalse_A	22192033	21553106	0	0
RomIntgChkDisTrue_A	22192033	139004	0	0
RstreqChkEsctimeout_A	22192033	4415	0	0
RstreqChkFsmterm_A	22192033	140	0	0
RstreqChkGlbesc_A	22192033	4415	0	0
RstreqChkMainpd_A	22192033	898016	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192620	5514	0	0
T14	14819	25	0	0
T15	15086	31	0	0
T16	1345	0	0	0
T20	254385	0	0	0
T21	3046	0	0	0
T26	4147	0	0	0
T44	7305	0	0	0
T45	1481	0	0	0
T57	13680	0	0	0
T90	1398	0	0	0
T101	0	257	0	0
T156	0	6	0	0
T157	0	13	0	0
T158	0	142	0	0
T159	0	33	0	0
T160	0	6	0	0
T161	0	6	0	0
T162	0	2	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	3085750	0	0
T1	1516	12	0	0
T2	6130	71	0	0
T3	5729	1123	0	0
T7	2431	13	0	0
T8	3082	270	0	0
T9	16579	4264	0	0
T10	4795	40	0	0
T11	4364	15	0	0
T12	9274	1101	0	0
T13	6586	1011	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5107847	323	0	0
T14	1309	3	0	0
T15	674	2	0	0
T16	222	3	0	0
T20	104541	0	0	0
T21	300	0	0	0
T26	383	0	0	0
T44	710	0	0	0
T45	510	0	0	0
T57	1170	0	0	0
T90	256	0	0	0
T156	0	2	0	0
T157	0	4	0	0
T158	0	3	0	0
T159	0	3	0	0
T160	0	5	0	0
T163	0	3	0	0
T164	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	57209	0	0
T1	1516	3	0	0
T2	6130	5	0	0
T3	5729	12	0	0
T7	2431	3	0	0
T8	3082	12	0	0
T9	16579	30	0	0
T10	4795	4	0	0
T11	4364	2	0	0
T12	9274	29	0	0
T13	6586	17	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	57259	0	0
T1	1516	3	0	0
T2	6130	5	0	0
T3	5729	12	0	0
T7	2431	3	0	0
T8	3082	13	0	0
T9	16579	30	0	0
T10	4795	4	0	0
T11	4364	2	0	0
T12	9274	29	0	0
T13	6586	17	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	27874	0	0
T14	14819	0	0	0
T17	4923	830	0	0
T18	47069	0	0	0
T19	35467	0	0	0
T26	0	865	0	0
T27	0	5	0	0
T28	0	197	0	0
T29	56805	0	0	0
T41	2615	0	0	0
T42	3023	0	0	0
T43	19133	0	0	0
T63	3010	0	0	0
T78	1080	0	0	0
T100	0	224	0	0
T137	0	1026	0	0
T165	0	10	0	0
T166	0	27	0	0
T167	0	291	0	0
T168	0	840	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	426219	0	0
T9	16579	365	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	0	0	0
T13	6586	0	0	0
T17	4923	876	0	0
T18	47069	368	0	0
T20	0	2358	0	0
T24	0	1560	0	0
T25	0	3495	0	0
T26	0	356	0	0
T27	0	1134	0	0
T29	56805	4136	0	0
T41	2615	0	0	0
T43	0	414	0	0
T78	1080	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	21553106	0	0
T1	1516	1441	0	0
T2	6130	6064	0	0
T3	5729	5637	0	0
T7	2431	2334	0	0
T8	3082	2124	0	0
T9	16579	16422	0	0
T10	4795	4711	0	0
T11	4364	4285	0	0
T12	9274	9111	0	0
T13	6586	6492	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	139004	0	0
T14	14819	0	0	0
T17	4923	387	0	0
T18	47069	0	0	0
T19	35467	0	0	0
T27	0	405	0	0
T28	0	102	0	0
T29	56805	0	0	0
T41	2615	0	0	0
T42	3023	0	0	0
T43	19133	0	0	0
T63	3010	0	0	0
T78	1080	0	0	0
T100	0	456	0	0
T137	0	756	0	0
T165	0	339	0	0
T167	0	762	0	0
T169	0	142	0	0
T170	0	14449	0	0
T171	0	1745	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	4415	0	0
T8	3082	9	0	0
T9	16579	0	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	8	0	0
T13	6586	0	0	0
T14	0	1	0	0
T17	4923	3	0	0
T18	47069	6	0	0
T20	0	77	0	0
T29	56805	0	0	0
T41	2615	8	0	0
T42	0	7	0	0
T44	0	6	0	0
T45	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	140	0	0
T4	22946	20	0	0
T5	0	20	0	0
T6	0	40	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	7444	0	0	0
T33	5223	0	0	0
T34	2149	0	0	0
T35	6267	0	0	0
T36	1194	0	0	0
T37	1143	0	0	0
T38	26483	0	0	0
T39	2365	0	0	0
T40	5022	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	4415	0	0
T8	3082	9	0	0
T9	16579	0	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	8	0	0
T13	6586	0	0	0
T14	0	1	0	0
T17	4923	3	0	0
T18	47069	6	0	0
T20	0	77	0	0
T29	56805	0	0	0
T41	2615	8	0	0
T42	0	7	0	0
T44	0	6	0	0
T45	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22192033	898016	0	0
T8	3082	103	0	0
T9	16579	1204	0	0
T10	4795	0	0	0
T11	4364	0	0	0
T12	9274	1130	0	0
T13	6586	0	0	0
T17	4923	994	0	0
T18	47069	616	0	0
T20	0	4378	0	0
T29	56805	7155	0	0
T41	2615	118	0	0
T42	0	93	0	0
T43	0	2153	0	0