Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	545440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208020

1

T1

1

T3

11

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	393146	1			T1	1		T2	1		T3	34
values[0x0]	180349	1			T3	10		T6	308		T7	22
values[0x1]	179965	1			T3	12		T6	316		T7	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	431746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

321714

1

T1

1

T3

24

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2646	1			T10	1		T11	48		T56	1
valid_sources[0x01]	3385	1			T11	43		T36	2		T38	3
valid_sources[0x02]	2347	1			T11	46		T12	2		T21	2
valid_sources[0x03]	2384	1			T11	44		T12	3		T21	6
valid_sources[0x04]	2552	1			T11	39		T38	1		T44	7
valid_sources[0x05]	3360	1			T5	1		T10	1		T11	51
valid_sources[0x06]	2153	1			T11	45		T38	2		T44	2
valid_sources[0x07]	5125	1			T3	2		T10	1		T11	39
valid_sources[0x08]	2366	1			T11	44		T12	3		T51	1
valid_sources[0x09]	2259	1			T11	36		T38	1		T44	3
valid_sources[0x0a]	2446	1			T11	51		T18	7		T56	3
valid_sources[0x0b]	2308	1			T4	1		T11	46		T56	1
valid_sources[0x0c]	4863	1			T6	13		T11	27		T12	1
valid_sources[0x0d]	3024	1			T3	2		T10	1		T11	31
valid_sources[0x0e]	2594	1			T11	47		T12	6		T56	1
valid_sources[0x0f]	2734	1			T11	46		T18	1		T56	2
valid_sources[0x10]	2830	1			T11	49		T12	1		T56	1
valid_sources[0x11]	3260	1			T3	1		T11	42		T18	3
valid_sources[0x12]	2509	1			T11	41		T51	7		T38	1
valid_sources[0x13]	3236	1			T11	48		T13	2		T44	5
valid_sources[0x14]	2275	1			T11	52		T56	2		T51	1
valid_sources[0x15]	3941	1			T11	39		T12	5		T56	1
valid_sources[0x16]	2704	1			T3	1		T11	55		T18	4
valid_sources[0x17]	2449	1			T7	1		T11	44		T36	1
valid_sources[0x18]	2226	1			T11	52		T12	2		T38	1
valid_sources[0x19]	3514	1			T2	1		T11	41		T56	1
valid_sources[0x1a]	2376	1			T11	35		T56	2		T13	12
valid_sources[0x1b]	2385	1			T3	2		T10	1		T11	44
valid_sources[0x1c]	2492	1			T11	43		T21	5		T13	13
valid_sources[0x1d]	3573	1			T11	46		T18	2		T51	2
valid_sources[0x1e]	2792	1			T6	22		T7	2		T11	29
valid_sources[0x1f]	3799	1			T11	50		T21	16		T37	4
valid_sources[0x20]	2260	1			T3	1		T11	45		T56	1
valid_sources[0x21]	2776	1			T3	1		T11	51		T18	1
valid_sources[0x22]	2876	1			T7	1		T11	42		T38	3
valid_sources[0x23]	2510	1			T11	25		T56	3		T21	11
valid_sources[0x24]	2697	1			T3	2		T11	48		T56	2
valid_sources[0x25]	2283	1			T3	1		T11	42		T51	1
valid_sources[0x26]	2222	1			T11	37		T18	1		T56	2
valid_sources[0x27]	5206	1			T3	1		T11	36		T18	1
valid_sources[0x28]	2442	1			T11	44		T38	4		T44	2
valid_sources[0x29]	3245	1			T3	1		T11	40		T36	1
valid_sources[0x2a]	2112	1			T11	51		T12	4		T56	1
valid_sources[0x2b]	3314	1			T7	1		T11	45		T56	1
valid_sources[0x2c]	2832	1			T11	58		T51	1		T21	6
valid_sources[0x2d]	3348	1			T11	35		T21	6		T60	2
valid_sources[0x2e]	2564	1			T11	41		T18	6		T21	11
valid_sources[0x2f]	3769	1			T11	53		T60	15		T62	1
valid_sources[0x30]	2342	1			T3	1		T11	43		T56	1
valid_sources[0x31]	2367	1			T10	1		T11	29		T12	1
valid_sources[0x32]	3786	1			T11	44		T12	3		T36	3
valid_sources[0x33]	2364	1			T11	45		T21	2		T61	2
valid_sources[0x34]	2516	1			T11	44		T12	2		T56	1
valid_sources[0x35]	2455	1			T6	12		T11	46		T56	2
valid_sources[0x36]	4559	1			T11	45		T18	2		T36	2
valid_sources[0x37]	3056	1			T11	47		T56	2		T21	4
valid_sources[0x38]	2455	1			T11	39		T56	1		T38	1
valid_sources[0x39]	4011	1			T11	49		T62	1		T38	6
valid_sources[0x3a]	3944	1			T7	10		T11	47		T21	14
valid_sources[0x3b]	2530	1			T11	43		T18	5		T12	1
valid_sources[0x3c]	3624	1			T11	51		T56	2		T38	4
valid_sources[0x3d]	3416	1			T11	42		T56	2		T36	1
valid_sources[0x3e]	2425	1			T7	7		T10	1		T11	43
valid_sources[0x3f]	3687	1			T7	1		T11	55		T56	1
valid_sources[0x40]	2731	1			T11	47		T18	4		T21	11
valid_sources[0x41]	4228	1			T7	1		T11	36		T36	1
valid_sources[0x42]	2845	1			T3	1		T10	1		T11	54
valid_sources[0x43]	4387	1			T6	934		T11	35		T18	1
valid_sources[0x44]	2386	1			T11	45		T21	18		T36	1
valid_sources[0x45]	3437	1			T11	48		T21	10		T36	1
valid_sources[0x46]	2367	1			T11	61		T38	3		T103	3
valid_sources[0x47]	4802	1			T3	1		T7	1		T11	44
valid_sources[0x48]	3764	1			T1	1		T7	3		T10	1
valid_sources[0x49]	2285	1			T11	41		T56	1		T21	4
valid_sources[0x4a]	2302	1			T11	63		T12	6		T51	3
valid_sources[0x4b]	2333	1			T11	37		T21	13		T38	4
valid_sources[0x4c]	2304	1			T11	48		T12	4		T56	3
valid_sources[0x4d]	2282	1			T11	50		T56	1		T61	1
valid_sources[0x4e]	4481	1			T11	53		T38	1		T44	4
valid_sources[0x4f]	2641	1			T7	13		T11	40		T51	4
valid_sources[0x50]	2389	1			T11	42		T18	1		T12	1
valid_sources[0x51]	2141	1			T10	1		T11	41		T56	2
valid_sources[0x52]	3758	1			T8	1		T10	1		T11	40
valid_sources[0x53]	2419	1			T7	3		T11	60		T56	1
valid_sources[0x54]	4644	1			T11	44		T18	1		T12	1
valid_sources[0x55]	2243	1			T11	49		T51	2		T21	6
valid_sources[0x56]	2349	1			T6	1		T10	1		T11	48
valid_sources[0x57]	3201	1			T9	12		T11	55		T18	3
valid_sources[0x58]	3276	1			T6	12		T11	33		T56	1
valid_sources[0x59]	2376	1			T7	1		T11	34		T12	1
valid_sources[0x5a]	2287	1			T3	3		T11	43		T36	1
valid_sources[0x5b]	3392	1			T10	1		T11	48		T56	1
valid_sources[0x5c]	2966	1			T7	4		T10	1		T11	50
valid_sources[0x5d]	2719	1			T3	3		T11	47		T13	14
valid_sources[0x5e]	4119	1			T11	49		T56	1		T37	4
valid_sources[0x5f]	2347	1			T6	1		T11	42		T36	1
valid_sources[0x60]	3168	1			T11	45		T18	2		T56	1
valid_sources[0x61]	2278	1			T11	49		T61	1		T38	1
valid_sources[0x62]	2512	1			T11	42		T56	3		T51	1
valid_sources[0x63]	5187	1			T11	27		T21	35		T38	1
valid_sources[0x64]	2606	1			T10	1		T11	42		T21	8
valid_sources[0x65]	2560	1			T11	37		T61	2		T37	1
valid_sources[0x66]	2636	1			T11	52		T18	2		T12	1
valid_sources[0x67]	3528	1			T3	1		T7	1		T11	39
valid_sources[0x68]	2344	1			T3	1		T11	42		T56	1
valid_sources[0x69]	2869	1			T11	39		T56	1		T51	1
valid_sources[0x6a]	4932	1			T11	44		T56	1		T60	14
valid_sources[0x6b]	2705	1			T3	1		T7	4		T11	51
valid_sources[0x6c]	2649	1			T11	45		T12	1		T56	2
valid_sources[0x6d]	3673	1			T11	55		T38	4		T44	3
valid_sources[0x6e]	2214	1			T3	3		T11	31		T56	1
valid_sources[0x6f]	2317	1			T6	12		T11	45		T51	1
valid_sources[0x70]	2423	1			T11	51		T56	1		T51	2
valid_sources[0x71]	2436	1			T11	45		T12	3		T51	2
valid_sources[0x72]	2978	1			T11	43		T56	1		T38	4
valid_sources[0x73]	5616	1			T11	53		T21	9		T61	1
valid_sources[0x74]	3611	1			T11	43		T35	352		T51	2
valid_sources[0x75]	3339	1			T7	8		T11	51		T12	2
valid_sources[0x76]	2563	1			T6	12		T11	51		T12	1
valid_sources[0x77]	2647	1			T3	1		T11	33		T56	3
valid_sources[0x78]	2706	1			T11	54		T12	8		T21	8
valid_sources[0x79]	4089	1			T10	1		T11	38		T56	1
valid_sources[0x7a]	2574	1			T11	32		T12	1		T38	3
valid_sources[0x7b]	3214	1			T7	7		T11	46		T21	1
valid_sources[0x7c]	2342	1			T11	62		T21	6		T62	1
valid_sources[0x7d]	2431	1			T6	24		T11	50		T18	1
valid_sources[0x7e]	2382	1			T11	31		T12	2		T21	2
valid_sources[0x7f]	2433	1			T11	37		T21	2		T38	3
valid_sources[0x80]	2465	1			T11	40		T18	5		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

104779

1

T1

1

T3

6

T5

1

values[0x0]

all_enables

biggest_size

67002

1

T3

4

T6

110

T7

12

values[0x1]

all_enables

biggest_size

36239

1

T3

1

T6

41

T7

5