SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35031 | 1 | T21 | 310 | T44 | 413 | T22 | 1 | ||||
others[1] | 34792 | 1 | T21 | 284 | T44 | 424 | T23 | 289 | ||||
others[2] | 35012 | 1 | T3 | 1 | T21 | 286 | T44 | 367 | ||||
others[3] | 58568 | 1 | T21 | 507 | T44 | 662 | T22 | 2 | ||||
false | 20232 | 1 | T3 | 2 | T6 | 32 | T11 | 256 | ||||
true | 30630 | 1 | T1 | 2 | T2 | 1 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35028 | 1 | T21 | 306 | T44 | 373 | T23 | 295 | ||||
others[1] | 35105 | 1 | T3 | 1 | T21 | 308 | T44 | 419 | ||||
others[2] | 34801 | 1 | T21 | 290 | T44 | 402 | T22 | 1 | ||||
others[3] | 58613 | 1 | T21 | 495 | T44 | 658 | T23 | 519 | ||||
false | 12715 | 1 | T3 | 2 | T6 | 16 | T11 | 128 | ||||
true | 23168 | 1 | T1 | 2 | T2 | 1 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 722 | 1 | T6 | 2 | T11 | 14 | T189 | 6 | ||||
others[1] | 690 | 1 | T6 | 4 | T11 | 10 | T36 | 2 | ||||
others[2] | 743 | 1 | T6 | 2 | T11 | 5 | T36 | 3 | ||||
others[3] | 1205 | 1 | T3 | 1 | T6 | 3 | T11 | 13 | ||||
false | 14503 | 1 | T1 | 2 | T2 | 1 | T3 | 4 | ||||
true | 4361 | 1 | T3 | 2 | T6 | 31 | T7 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |