Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T11
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T39,T81

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	26842574	6379	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	26842574	268445	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	26842574	11145243	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	26842574	268420	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	26842574	6379	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	26842574	268445	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	26842574	11145243	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	26842574	268420	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	6379	0	0
T6	32238	7	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	1	0	0
T11	314691	75	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	15	0	0
T35	0	11	0	0
T38	0	9	0	0
T39	1326	3	0	0
T44	0	27	0	0
T62	0	1	0	0
T80	1963	0	0	0
T81	0	7	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	268445	0	0
T6	32238	180	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	12	0	0
T11	314691	2128	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	384	0	0
T35	0	413	0	0
T38	0	161	0	0
T39	1326	315	0	0
T44	0	466	0	0
T62	0	10	0	0
T80	1963	0	0	0
T81	0	232	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	11145243	0	0
T6	32238	10013	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	1717	0	0
T11	314691	138179	0	0
T12	13624	6733	0	0
T18	4192	0	0	0
T21	0	6192	0	0
T35	0	8273	0	0
T39	1326	591	0	0
T51	0	1841	0	0
T56	0	2717	0	0
T80	1963	334	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	268420	0	0
T6	32238	180	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	12	0	0
T11	314691	2118	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	384	0	0
T35	0	413	0	0
T38	0	161	0	0
T39	1326	315	0	0
T44	0	466	0	0
T62	0	10	0	0
T80	1963	0	0	0
T81	0	232	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	6379	0	0
T6	32238	7	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	1	0	0
T11	314691	75	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	15	0	0
T35	0	11	0	0
T38	0	9	0	0
T39	1326	3	0	0
T44	0	27	0	0
T62	0	1	0	0
T80	1963	0	0	0
T81	0	7	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	268445	0	0
T6	32238	180	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	12	0	0
T11	314691	2128	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	384	0	0
T35	0	413	0	0
T38	0	161	0	0
T39	1326	315	0	0
T44	0	466	0	0
T62	0	10	0	0
T80	1963	0	0	0
T81	0	232	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	11145243	0	0
T6	32238	10013	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	1717	0	0
T11	314691	138179	0	0
T12	13624	6733	0	0
T18	4192	0	0	0
T21	0	6192	0	0
T35	0	8273	0	0
T39	1326	591	0	0
T51	0	1841	0	0
T56	0	2717	0	0
T80	1963	334	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	268420	0	0
T6	32238	180	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	12	0	0
T11	314691	2118	0	0
T12	13624	0	0	0
T18	4192	0	0	0
T21	0	384	0	0
T35	0	413	0	0
T38	0	161	0	0
T39	1326	315	0	0
T44	0	466	0	0
T62	0	10	0	0
T80	1963	0	0	0
T81	0	232	0	0