Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27418674	16555	0	0
intr_enable_rd_A	27418674	54619	0	0
reset_en_rd_A	27418674	1401	0	0
reset_en_regwen_rd_A	27418674	1350	0	0
wake_info_capture_dis_rd_A	27418674	1354	0	0
wakeup_en_rd_A	27418674	1627	0	0
wakeup_en_regwen_rd_A	27418674	1205	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	16555	0	0
T11	314691	6	0	0
T12	13624	0	0	0
T13	2761	0	0	0
T18	4192	0	0	0
T19	0	42	0	0
T20	0	8	0	0
T21	17916	0	0	0
T35	13738	0	0	0
T39	1326	0	0	0
T48	0	134	0	0
T49	0	116	0	0
T50	0	59	0	0
T51	2318	0	0	0
T56	7602	0	0	0
T80	1963	0	0	0
T83	0	104	0	0
T139	0	10	0	0
T140	0	12	0	0
T141	0	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	54619	0	0
T6	32238	202	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	9	0	0
T10	2665	10	0	0
T11	314691	0	0	0
T12	13624	49	0	0
T18	4192	0	0	0
T22	0	19	0	0
T23	0	181	0	0
T37	0	54	0	0
T39	1326	0	0	0
T56	0	45	0	0
T57	0	12	0	0
T62	0	13	0	0
T80	1963	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	1401	0	0
T19	486285	14	0	0
T20	570615	4	0	0
T85	0	6	0	0
T140	0	3	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	12	0	0
T145	0	28	0	0
T146	0	8	0	0
T147	0	16	0	0
T148	10669	0	0	0
T149	11814	0	0	0
T150	4226	0	0	0
T151	30590	0	0	0
T152	1777	0	0	0
T153	15445	0	0	0
T154	7366	0	0	0
T155	1513	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	1350	0	0
T19	486285	7	0	0
T20	570615	5	0	0
T85	0	6	0	0
T88	0	10	0	0
T140	0	14	0	0
T142	0	15	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	13	0	0
T147	0	16	0	0
T148	10669	0	0	0
T149	11814	0	0	0
T150	4226	0	0	0
T151	30590	0	0	0
T152	1777	0	0	0
T153	15445	0	0	0
T154	7366	0	0	0
T155	1513	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	1354	0	0
T19	486285	5	0	0
T20	570615	4	0	0
T85	0	8	0	0
T88	0	15	0	0
T140	0	4	0	0
T142	0	13	0	0
T144	0	6	0	0
T145	0	20	0	0
T146	0	8	0	0
T147	0	4	0	0
T148	10669	0	0	0
T149	11814	0	0	0
T150	4226	0	0	0
T151	30590	0	0	0
T152	1777	0	0	0
T153	15445	0	0	0
T154	7366	0	0	0
T155	1513	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	1627	0	0
T20	570615	8	0	0
T52	0	11	0	0
T63	0	11	0	0
T85	0	4	0	0
T88	0	8	0	0
T140	0	15	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	22	0	0
T151	30590	0	0	0
T152	1777	0	0	0
T153	15445	0	0	0
T154	7366	0	0	0
T155	1513	0	0	0
T156	0	16	0	0
T157	1434	0	0	0
T158	1978	0	0	0
T159	1246	0	0	0
T160	54900	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27418674	1205	0	0
T19	486285	4	0	0
T20	570615	5	0	0
T85	0	6	0	0
T88	0	15	0	0
T140	0	7	0	0
T142	0	6	0	0
T144	0	11	0	0
T145	0	10	0	0
T146	0	13	0	0
T148	10669	0	0	0
T149	11814	0	0	0
T150	4226	0	0	0
T151	30590	0	0	0
T152	1777	0	0	0
T153	15445	0	0	0
T154	7366	0	0	0
T155	1513	0	0	0
T156	0	7	0	0