Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	80527722	156076	0	0
StatusRise_A	80527722	173919	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80527722	156076	0	0
T1	1587	3	0	0
T2	46581	3	0	0
T3	4593	15	0	0
T4	3894	0	0	0
T5	1995	3	0	0
T6	96714	334	0	0
T7	16335	39	0	0
T8	5676	0	0	0
T9	4272	6	0	0
T10	7995	6	0	0
T11	0	2525	0	0
T39	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80527722	173919	0	0
T1	1587	9	0	0
T2	46581	6	0	0
T3	4593	18	0	0
T4	3894	15	0	0
T5	1995	9	0	0
T6	96714	362	0	0
T7	16335	45	0	0
T8	5676	9	0	0
T9	4272	9	0	0
T10	7995	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26842574	57900	0	0
StatusRise_A	26842574	64342	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	57900	0	0
T1	529	1	0	0
T2	15527	1	0	0
T3	1531	5	0	0
T4	1298	0	0	0
T5	665	1	0	0
T6	32238	122	0	0
T7	5445	13	0	0
T8	1892	0	0	0
T9	1424	2	0	0
T10	2665	2	0	0
T11	0	933	0	0
T39	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	64342	0	0
T1	529	3	0	0
T2	15527	2	0	0
T3	1531	6	0	0
T4	1298	5	0	0
T5	665	3	0	0
T6	32238	132	0	0
T7	5445	15	0	0
T8	1892	3	0	0
T9	1424	3	0	0
T10	2665	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26842574	57900	0	0
StatusRise_A	26842574	64343	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	57900	0	0
T1	529	1	0	0
T2	15527	1	0	0
T3	1531	5	0	0
T4	1298	0	0	0
T5	665	1	0	0
T6	32238	122	0	0
T7	5445	13	0	0
T8	1892	0	0	0
T9	1424	2	0	0
T10	2665	2	0	0
T11	0	933	0	0
T39	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	64343	0	0
T1	529	3	0	0
T2	15527	2	0	0
T3	1531	6	0	0
T4	1298	5	0	0
T5	665	3	0	0
T6	32238	132	0	0
T7	5445	15	0	0
T8	1892	3	0	0
T9	1424	3	0	0
T10	2665	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26842574	40276	0	0
StatusRise_A	26842574	45234	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	40276	0	0
T1	529	1	0	0
T2	15527	1	0	0
T3	1531	5	0	0
T4	1298	0	0	0
T5	665	1	0	0
T6	32238	90	0	0
T7	5445	13	0	0
T8	1892	0	0	0
T9	1424	2	0	0
T10	2665	2	0	0
T11	0	659	0	0
T39	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	45234	0	0
T1	529	3	0	0
T2	15527	2	0	0
T3	1531	6	0	0
T4	1298	5	0	0
T5	665	3	0	0
T6	32238	98	0	0
T7	5445	15	0	0
T8	1892	3	0	0
T9	1424	3	0	0
T10	2665	3	0	0