Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26843163	6631	0	0
EscTimeoutStoppedByClReset_A	26842574	3798936	0	0
EscTimeoutTriggersReset_A	4995036	328	0	0
RomAllowActiveState_A	26842574	63938	0	0
RomAllowCheckGoodState_A	26842574	63989	0	0
RomBlockActiveState_A	26842574	23713	0	0
RomBlockCheckGoodState_A	26842574	420426	0	0
RomIntgChkDisFalse_A	26842574	26192690	0	0
RomIntgChkDisTrue_A	26842574	94245	0	0
RstreqChkEsctimeout_A	26842574	4726	0	0
RstreqChkFsmterm_A	26842574	200	0	0
RstreqChkGlbesc_A	26842574	4726	0	0
RstreqChkMainpd_A	26842574	1032844	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26843163	6631	0	0
T2	15528	216	0	0
T3	1532	0	0	0
T4	1299	0	0	0
T5	666	0	0	0
T6	32239	0	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1425	0	0	0
T10	2665	0	0	0
T11	314692	0	0	0
T106	0	60	0	0
T161	0	2	0	0
T162	0	270	0	0
T163	0	5	0	0
T164	0	51	0	0
T165	0	5	0	0
T166	0	95	0	0
T167	0	230	0	0
T168	0	62	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	3798936	0	0
T1	529	14	0	0
T2	15527	48	0	0
T3	1531	133	0	0
T4	1298	23	0	0
T5	665	25	0	0
T6	32238	3480	0	0
T7	5445	572	0	0
T8	1892	0	0	0
T9	1424	25	0	0
T10	2665	34	0	0
T11	0	39816	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4995036	328	0	0
T1	780	14	0	0
T2	195	3	0	0
T3	689	0	0	0
T4	367	0	0	0
T5	323	7	0	0
T6	10060	0	0	0
T7	414	0	0	0
T8	267	0	0	0
T9	438	0	0	0
T10	237	0	0	0
T101	0	3	0	0
T106	0	2	0	0
T161	0	6	0	0
T162	0	3	0	0
T163	0	4	0	0
T169	0	2	0	0
T170	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	63938	0	0
T1	529	3	0	0
T2	15527	2	0	0
T3	1531	6	0	0
T4	1298	5	0	0
T5	665	3	0	0
T6	32238	132	0	0
T7	5445	15	0	0
T8	1892	3	0	0
T9	1424	3	0	0
T10	2665	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	63989	0	0
T1	529	3	0	0
T2	15527	2	0	0
T3	1531	6	0	0
T4	1298	5	0	0
T5	665	3	0	0
T6	32238	132	0	0
T7	5445	15	0	0
T8	1892	3	0	0
T9	1424	3	0	0
T10	2665	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	23713	0	0
T3	1531	92	0	0
T4	1298	0	0	0
T5	665	0	0	0
T6	32238	0	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	314691	0	0	0
T21	0	12	0	0
T22	0	1063	0	0
T39	1326	0	0	0
T44	0	4	0	0
T104	0	248	0	0
T171	0	1330	0	0
T172	0	720	0	0
T173	0	2	0	0
T174	0	18	0	0
T175	0	744	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	420426	0	0
T3	1531	5	0	0
T4	1298	0	0	0
T5	665	0	0	0
T6	32238	366	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	314691	2935	0	0
T21	0	1280	0	0
T22	0	869	0	0
T35	0	459	0	0
T38	0	413	0	0
T39	1326	0	0	0
T44	0	860	0	0
T81	0	207	0	0
T176	0	344	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	26192690	0	0
T1	529	355	0	0
T2	15527	15474	0	0
T3	1531	1413	0	0
T4	1298	887	0	0
T5	665	522	0	0
T6	32238	31544	0	0
T7	5445	5293	0	0
T8	1892	1642	0	0
T9	1424	1337	0	0
T10	2665	2610	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	94245	0	0
T3	1531	56	0	0
T4	1298	0	0	0
T5	665	0	0	0
T6	32238	0	0	0
T7	5445	0	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	314691	0	0	0
T21	0	642	0	0
T22	0	1669	0	0
T23	0	2485	0	0
T39	1326	0	0	0
T104	0	203	0	0
T171	0	2034	0	0
T172	0	250	0	0
T174	0	157	0	0
T175	0	1865	0	0
T177	0	265	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	4726	0	0
T1	529	1	0	0
T2	15527	1	0	0
T3	1531	2	0	0
T4	1298	0	0	0
T5	665	1	0	0
T6	32238	30	0	0
T7	5445	3	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	0	71	0	0
T18	0	7	0	0
T36	0	6	0	0
T40	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	200	0	0
T15	42614	40	0	0
T16	0	40	0	0
T17	0	40	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	18023	0	0	0
T27	16180	0	0	0
T28	2860	0	0	0
T29	3082	0	0	0
T30	6981	0	0	0
T31	1327	0	0	0
T32	15170	0	0	0
T33	5900	0	0	0
T34	2422	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	4726	0	0
T1	529	1	0	0
T2	15527	1	0	0
T3	1531	2	0	0
T4	1298	0	0	0
T5	665	1	0	0
T6	32238	30	0	0
T7	5445	3	0	0
T8	1892	0	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	0	71	0	0
T18	0	7	0	0
T36	0	6	0	0
T40	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26842574	1032844	0	0
T3	1531	86	0	0
T4	1298	15	0	0
T5	665	0	0	0
T6	32238	1341	0	0
T7	5445	536	0	0
T8	1892	12	0	0
T9	1424	0	0	0
T10	2665	0	0	0
T11	314691	5458	0	0
T18	0	138	0	0
T21	0	1313	0	0
T35	0	1596	0	0
T36	0	87	0	0
T39	1326	0	0	0