Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	528011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208767

1

T1

39

T3

6

T4

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	393263	1			T1	182		T2	1		T3	15
values[0x0]	171554	1			T1	34		T3	6		T4	11
values[0x1]	171961	1			T1	28		T3	4		T4	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	417975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

318803

1

T1

102

T3

7

T4

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6618	1			T5	26		T9	22		T43	1
valid_sources[0x01]	3073	1			T5	6		T7	4		T9	10
valid_sources[0x02]	2224	1			T1	4		T5	5		T7	7
valid_sources[0x03]	4009	1			T5	2		T7	5		T43	1
valid_sources[0x04]	3447	1			T5	1		T7	7		T9	12
valid_sources[0x05]	3167	1			T5	11		T7	3		T21	1
valid_sources[0x06]	3179	1			T1	1		T7	4		T21	1
valid_sources[0x07]	5234	1			T1	4		T5	3		T7	7
valid_sources[0x08]	2289	1			T5	6		T7	6		T39	3
valid_sources[0x09]	2283	1			T7	2		T36	2		T15	1
valid_sources[0x0a]	2368	1			T1	2		T5	1		T42	1
valid_sources[0x0b]	2772	1			T7	4		T36	2		T22	45
valid_sources[0x0c]	2279	1			T5	5		T7	2		T14	2
valid_sources[0x0d]	2780	1			T5	2		T7	3		T21	1
valid_sources[0x0e]	2431	1			T1	1		T5	4		T6	8
valid_sources[0x0f]	4345	1			T5	10		T7	3		T21	2
valid_sources[0x10]	2565	1			T1	1		T36	6		T22	36
valid_sources[0x11]	2451	1			T1	1		T5	1		T7	2
valid_sources[0x12]	2468	1			T1	2		T4	1		T7	4
valid_sources[0x13]	4234	1			T1	1		T4	1		T5	9
valid_sources[0x14]	2352	1			T4	1		T5	8		T7	7
valid_sources[0x15]	2389	1			T1	1		T7	2		T14	1
valid_sources[0x16]	2402	1			T1	1		T4	1		T7	3
valid_sources[0x17]	2460	1			T5	4		T7	4		T9	6
valid_sources[0x18]	2837	1			T1	1		T4	2		T7	1
valid_sources[0x19]	3272	1			T1	2		T4	1		T5	6
valid_sources[0x1a]	2549	1			T5	1		T42	1		T36	4
valid_sources[0x1b]	2508	1			T5	5		T7	3		T42	1
valid_sources[0x1c]	2478	1			T1	4		T5	1		T7	5
valid_sources[0x1d]	4687	1			T1	2		T5	6		T7	5
valid_sources[0x1e]	2329	1			T1	1		T5	1		T6	1
valid_sources[0x1f]	2536	1			T5	2		T7	1		T14	1
valid_sources[0x20]	2423	1			T4	1		T5	8		T7	3
valid_sources[0x21]	7958	1			T5	5		T7	11		T13	1
valid_sources[0x22]	3423	1			T1	3		T5	1		T7	2
valid_sources[0x23]	2368	1			T4	1		T5	5		T7	1
valid_sources[0x24]	3547	1			T5	1		T7	2		T21	5
valid_sources[0x25]	5454	1			T1	1		T5	4		T14	1
valid_sources[0x26]	2312	1			T5	5		T7	10		T42	1
valid_sources[0x27]	2428	1			T1	1		T5	1		T7	4
valid_sources[0x28]	2066	1			T5	1		T7	1		T14	1
valid_sources[0x29]	2261	1			T1	3		T4	1		T6	9
valid_sources[0x2a]	2903	1			T5	1		T7	7		T36	6
valid_sources[0x2b]	2290	1			T1	1		T43	6		T36	10
valid_sources[0x2c]	2413	1			T1	1		T5	2		T7	1
valid_sources[0x2d]	3149	1			T1	1		T5	1		T7	8
valid_sources[0x2e]	2414	1			T5	9		T6	9		T7	4
valid_sources[0x2f]	2583	1			T5	1		T21	1		T13	1
valid_sources[0x30]	2596	1			T1	2		T5	11		T6	4
valid_sources[0x31]	4247	1			T1	3		T5	8		T7	2
valid_sources[0x32]	3139	1			T1	3		T4	1		T7	9
valid_sources[0x33]	2866	1			T5	6		T7	4		T9	1
valid_sources[0x34]	2581	1			T4	1		T5	20		T7	6
valid_sources[0x35]	2229	1			T1	1		T5	1		T7	5
valid_sources[0x36]	2522	1			T7	10		T42	1		T43	1
valid_sources[0x37]	2061	1			T1	1		T13	3		T42	2
valid_sources[0x38]	3302	1			T4	1		T5	13		T7	3
valid_sources[0x39]	2449	1			T1	3		T7	10		T43	3
valid_sources[0x3a]	3333	1			T1	1		T7	5		T21	1
valid_sources[0x3b]	2464	1			T1	2		T4	1		T5	10
valid_sources[0x3c]	3668	1			T1	2		T5	1		T42	1
valid_sources[0x3d]	2132	1			T5	5		T7	2		T13	1
valid_sources[0x3e]	2513	1			T7	7		T9	27		T42	1
valid_sources[0x3f]	2654	1			T1	1		T5	3		T7	1
valid_sources[0x40]	2296	1			T1	2		T4	2		T5	3
valid_sources[0x41]	2588	1			T1	1		T7	4		T42	2
valid_sources[0x42]	3310	1			T4	1		T7	8		T42	2
valid_sources[0x43]	3319	1			T5	3		T7	3		T42	1
valid_sources[0x44]	2870	1			T1	1		T7	2		T14	1
valid_sources[0x45]	2192	1			T5	4		T7	6		T9	4
valid_sources[0x46]	2974	1			T1	1		T7	3		T9	8
valid_sources[0x47]	2360	1			T1	1		T14	2		T36	3
valid_sources[0x48]	2454	1			T1	3		T5	8		T42	1
valid_sources[0x49]	2244	1			T1	1		T5	5		T7	5
valid_sources[0x4a]	2508	1			T1	1		T5	4		T7	1
valid_sources[0x4b]	2726	1			T1	2		T9	6		T21	2
valid_sources[0x4c]	2230	1			T7	4		T9	1		T36	3
valid_sources[0x4d]	2931	1			T1	1		T5	7		T7	3
valid_sources[0x4e]	2751	1			T4	2		T7	1		T21	6
valid_sources[0x4f]	2469	1			T5	1		T7	1		T42	1
valid_sources[0x50]	3124	1			T1	3		T7	6		T21	3
valid_sources[0x51]	2360	1			T1	1		T5	4		T6	1
valid_sources[0x52]	2302	1			T7	5		T42	2		T36	1
valid_sources[0x53]	2544	1			T1	1		T5	12		T7	8
valid_sources[0x54]	2950	1			T5	1		T43	1		T36	2
valid_sources[0x55]	2407	1			T2	1		T4	1		T5	4
valid_sources[0x56]	5031	1			T5	2		T7	1		T9	28
valid_sources[0x57]	3449	1			T7	3		T9	1		T21	3
valid_sources[0x58]	2306	1			T1	3		T4	1		T5	3
valid_sources[0x59]	2643	1			T1	1		T3	25		T4	1
valid_sources[0x5a]	2584	1			T1	1		T5	2		T6	1
valid_sources[0x5b]	2370	1			T5	1		T7	3		T42	1
valid_sources[0x5c]	2407	1			T1	3		T7	2		T21	1
valid_sources[0x5d]	3338	1			T7	1		T42	1		T36	3
valid_sources[0x5e]	2223	1			T1	3		T7	4		T21	3
valid_sources[0x5f]	2064	1			T4	1		T6	3		T7	5
valid_sources[0x60]	2663	1			T1	2		T5	6		T7	2
valid_sources[0x61]	3041	1			T5	5		T7	7		T21	1
valid_sources[0x62]	3771	1			T1	2		T5	2		T7	5
valid_sources[0x63]	2362	1			T1	2		T4	1		T36	8
valid_sources[0x64]	2265	1			T1	1		T7	2		T42	1
valid_sources[0x65]	2827	1			T5	5		T7	4		T13	4
valid_sources[0x66]	2492	1			T1	1		T7	3		T21	1
valid_sources[0x67]	2651	1			T4	1		T5	7		T7	6
valid_sources[0x68]	2699	1			T7	1		T9	1		T14	1
valid_sources[0x69]	3315	1			T1	1		T5	2		T6	1
valid_sources[0x6a]	2419	1			T7	3		T9	11		T14	1
valid_sources[0x6b]	2568	1			T5	1		T7	4		T42	1
valid_sources[0x6c]	2364	1			T1	1		T5	2		T7	3
valid_sources[0x6d]	3537	1			T4	1		T5	3		T42	2
valid_sources[0x6e]	3323	1			T5	7		T7	1		T43	3
valid_sources[0x6f]	2415	1			T1	1		T5	4		T7	3
valid_sources[0x70]	4955	1			T1	1		T5	1		T7	8
valid_sources[0x71]	2867	1			T1	1		T6	6		T7	4
valid_sources[0x72]	2218	1			T4	1		T7	6		T9	4
valid_sources[0x73]	2694	1			T1	1		T5	1		T6	1
valid_sources[0x74]	2262	1			T5	10		T7	1		T42	4
valid_sources[0x75]	2628	1			T4	1		T5	2		T7	6
valid_sources[0x76]	2181	1			T1	1		T4	1		T6	1
valid_sources[0x77]	2660	1			T1	1		T5	20		T7	2
valid_sources[0x78]	2442	1			T1	2		T4	1		T6	6
valid_sources[0x79]	2140	1			T5	1		T7	3		T43	1
valid_sources[0x7a]	2335	1			T5	5		T7	1		T43	3
valid_sources[0x7b]	2394	1			T1	1		T7	7		T9	9
valid_sources[0x7c]	3428	1			T7	10		T42	1		T36	2
valid_sources[0x7d]	3163	1			T1	2		T5	6		T7	2
valid_sources[0x7e]	2383	1			T1	1		T4	1		T5	2
valid_sources[0x7f]	3277	1			T1	1		T7	2		T42	1
valid_sources[0x80]	3115	1			T1	3		T5	5		T7	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

109943

1

T1

20

T3

4

T4

11

values[0x0]

all_enables

biggest_size

64105

1

T1

14

T3

1

T4

4

values[0x1]

all_enables

biggest_size

34719

1

T1

5

T3

1

T4

3