SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35048 | 1 | T5 | 293 | T7 | 420 | T36 | 313 | ||||
others[1] | 34736 | 1 | T5 | 296 | T7 | 376 | T36 | 272 | ||||
others[2] | 35035 | 1 | T5 | 304 | T7 | 372 | T36 | 314 | ||||
others[3] | 58592 | 1 | T5 | 501 | T7 | 683 | T36 | 499 | ||||
false | 20046 | 1 | T5 | 50 | T7 | 50 | T9 | 8 | ||||
true | 30150 | 1 | T1 | 1 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35024 | 1 | T5 | 303 | T7 | 411 | T13 | 1 | ||||
others[1] | 34976 | 1 | T5 | 281 | T7 | 381 | T36 | 282 | ||||
others[2] | 35167 | 1 | T5 | 310 | T7 | 414 | T36 | 312 | ||||
others[3] | 58400 | 1 | T5 | 512 | T7 | 654 | T13 | 1 | ||||
false | 12610 | 1 | T5 | 50 | T7 | 50 | T9 | 4 | ||||
true | 22791 | 1 | T1 | 1 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 698 | 1 | T1 | 4 | T42 | 6 | T22 | 9 | ||||
others[1] | 654 | 1 | T1 | 5 | T42 | 12 | T22 | 7 | ||||
others[2] | 714 | 1 | T1 | 4 | T42 | 4 | T22 | 13 | ||||
others[3] | 1135 | 1 | T1 | 12 | T13 | 2 | T14 | 1 | ||||
false | 13710 | 1 | T1 | 5 | T2 | 6 | T3 | 1 | ||||
true | 4006 | 1 | T1 | 4 | T13 | 2 | T14 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |