Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25066350	15013	0	0
intr_enable_rd_A	25066350	26539	0	0
reset_en_rd_A	25066350	1462	0	0
reset_en_regwen_rd_A	25066350	1417	0	0
wake_info_capture_dis_rd_A	25066350	1398	0	0
wakeup_en_rd_A	25066350	1834	0	0
wakeup_en_regwen_rd_A	25066350	1399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	15013	0	0
T22	625767	29	0	0
T23	280968	4	0	0
T24	637540	143	0	0
T37	35042	0	0	0
T38	2872	0	0	0
T40	15731	0	0	0
T41	1282	0	0	0
T44	0	26	0	0
T46	0	7	0	0
T86	2179	0	0	0
T87	17078	0	0	0
T92	2857	0	0	0
T127	0	13	0	0
T128	0	16	0	0
T129	0	60	0	0
T130	0	10	0	0
T131	0	34	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	26539	0	0
T1	6833	44	0	0
T2	3695	0	0	0
T3	1415	6	0	0
T4	2259	0	0	0
T5	27090	0	0	0
T6	1295	0	0	0
T7	15583	0	0	0
T8	737	0	0	0
T9	9452	137	0	0
T10	2650	0	0	0
T23	0	2551	0	0
T88	0	38	0	0
T95	0	39	0	0
T124	0	27	0	0
T132	0	48	0	0
T133	0	4	0	0
T134	0	87	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	1462	0	0
T58	0	17	0	0
T60	0	2	0	0
T68	0	47	0	0
T71	0	7	0	0
T77	0	36	0	0
T111	0	2	0	0
T135	208111	9	0	0
T136	0	12	0	0
T137	0	1	0	0
T138	0	20	0	0
T139	3293	0	0	0
T140	2190	0	0	0
T141	1806	0	0	0
T142	4209	0	0	0
T143	185451	0	0	0
T144	175477	0	0	0
T145	2353	0	0	0
T146	2057	0	0	0
T147	15232	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	1417	0	0
T58	0	38	0	0
T60	0	6	0	0
T68	0	29	0	0
T71	0	9	0	0
T77	0	57	0	0
T136	0	10	0	0
T137	0	13	0	0
T138	0	29	0	0
T148	126274	4	0	0
T149	0	13	0	0
T150	13435	0	0	0
T151	33149	0	0	0
T152	2550	0	0	0
T153	3554	0	0	0
T154	4627	0	0	0
T155	2046	0	0	0
T156	3357	0	0	0
T157	6910	0	0	0
T158	8407	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	1398	0	0
T23	280968	14	0	0
T24	637540	0	0	0
T37	35042	0	0	0
T38	2872	0	0	0
T40	15731	0	0	0
T41	1282	0	0	0
T58	0	6	0	0
T60	0	12	0	0
T68	0	39	0	0
T71	0	8	0	0
T86	2179	0	0	0
T87	17078	0	0	0
T92	2857	0	0	0
T111	0	4	0	0
T135	0	2	0	0
T136	0	12	0	0
T137	0	5	0	0
T148	0	5	0	0
T159	2172	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	1834	0	0
T23	280968	5	0	0
T24	637540	0	0	0
T37	35042	0	0	0
T38	2872	0	0	0
T40	15731	0	0	0
T41	1282	0	0	0
T58	0	11	0	0
T60	0	9	0	0
T68	0	40	0	0
T77	0	18	0	0
T86	2179	0	0	0
T87	17078	0	0	0
T92	2857	0	0	0
T136	0	3	0	0
T137	0	9	0	0
T138	0	34	0	0
T148	0	1	0	0
T149	0	41	0	0
T159	2172	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25066350	1399	0	0
T23	280968	3	0	0
T24	637540	0	0	0
T37	35042	0	0	0
T38	2872	0	0	0
T40	15731	0	0	0
T41	1282	0	0	0
T58	0	18	0	0
T60	0	9	0	0
T68	0	37	0	0
T71	0	16	0	0
T77	0	51	0	0
T86	2179	0	0	0
T87	17078	0	0	0
T92	2857	0	0	0
T111	0	1	0	0
T136	0	12	0	0
T137	0	17	0	0
T148	0	1	0	0
T159	2172	0	0	0