Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73329351	147631	0	0
StatusRise_A	73329351	164680	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73329351	147631	0	0
T1	20499	12	0	0
T2	11085	0	0	0
T3	4245	6	0	0
T4	6777	11	0	0
T5	81270	200	0	0
T6	3885	24	0	0
T7	46749	203	0	0
T8	2211	3	0	0
T9	28356	103	0	0
T10	7950	0	0	0
T13	0	15	0	0
T21	0	25	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73329351	164680	0	0
T1	20499	15	0	0
T2	11085	18	0	0
T3	4245	9	0	0
T4	6777	14	0	0
T5	81270	205	0	0
T6	3885	26	0	0
T7	46749	205	0	0
T8	2211	9	0	0
T9	28356	117	0	0
T10	7950	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24443117	54900	0	0
StatusRise_A	24443117	61066	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	54900	0	0
T1	6833	4	0	0
T2	3695	0	0	0
T3	1415	2	0	0
T4	2259	4	0	0
T5	27090	82	0	0
T6	1295	9	0	0
T7	15583	83	0	0
T8	737	1	0	0
T9	9452	38	0	0
T10	2650	0	0	0
T13	0	5	0	0
T21	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	61066	0	0
T1	6833	5	0	0
T2	3695	6	0	0
T3	1415	3	0	0
T4	2259	5	0	0
T5	27090	84	0	0
T6	1295	10	0	0
T7	15583	84	0	0
T8	737	3	0	0
T9	9452	43	0	0
T10	2650	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24443117	54900	0	0
StatusRise_A	24443117	61066	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	54900	0	0
T1	6833	4	0	0
T2	3695	0	0	0
T3	1415	2	0	0
T4	2259	4	0	0
T5	27090	82	0	0
T6	1295	9	0	0
T7	15583	83	0	0
T8	737	1	0	0
T9	9452	38	0	0
T10	2650	0	0	0
T13	0	5	0	0
T21	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	61066	0	0
T1	6833	5	0	0
T2	3695	6	0	0
T3	1415	3	0	0
T4	2259	5	0	0
T5	27090	84	0	0
T6	1295	10	0	0
T7	15583	84	0	0
T8	737	3	0	0
T9	9452	43	0	0
T10	2650	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24443117	37831	0	0
StatusRise_A	24443117	42548	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	37831	0	0
T1	6833	4	0	0
T2	3695	0	0	0
T3	1415	2	0	0
T4	2259	3	0	0
T5	27090	36	0	0
T6	1295	6	0	0
T7	15583	37	0	0
T8	737	1	0	0
T9	9452	27	0	0
T10	2650	0	0	0
T13	0	5	0	0
T21	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24443117	42548	0	0
T1	6833	5	0	0
T2	3695	6	0	0
T3	1415	3	0	0
T4	2259	4	0	0
T5	27090	37	0	0
T6	1295	6	0	0
T7	15583	37	0	0
T8	737	3	0	0
T9	9452	31	0	0
T10	2650	4	0	0